Process-Oriented Stress Modeling and Stress Evolution During Cu/Low-K BEOL Processing
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Process-Oriented Stress Modeling and Stress Evolution During Cu/Low-K BEOL Processing Charlie Jun Zhai, Paul R. Besser, Frank Feustel, Amit Marathe, Richard C. Blish II Advanced Micro Devices, Inc 1 AMD Place, MS 79, Sunnyvale, CA 94088-3453 ABSTRACT The damascene fabrication method and the introduction of low-K dielectrics present a host of reliability challenges to Cu interconnects and fundamentally change the mechanical stress state of Cu lines. In order to capture the effect of individual process steps on the stress evolution in the BEoL (Back End of Line), a process-oriented finite element modeling (FEM) approach was developed. In this model, the complete stress history at any step of BEoL can be simulated as a dual damascene Cu structure is fabricated. The inputs to the model include the temperature profile during each process step and materials constants. The modeling results are verified in two ways: through wafer-curvature measurement during multiple film deposition processes and with X-Ray diffraction to measure the mechanical stress state of the Cu interconnect lines fabricated using 0.13um CMOS technology. The Cu line stress evolution is simulated during the process of multi-step processing for a dual damascene Cu/low-K structure. It is shown that the in-plane stress of Cu lines is nearly independent of subsequent processes, while the out-of-plane stress increases considerably with the subsequent process steps. INTRODUCTION Conventional stress measurement methods include wafer curvature and X-ray diffraction. Stress measurement, which is limited to simple test structures, has insufficient spatial resolution to determine the detailed stress distribution in a complicated interconnect system. Hence, finite element stress modeling has been extensively used for detailed stress analysis. [1-4] During the last few years, X-ray diffraction measurements [3-6] have been used to validate stress modeling. Traditionally, mechanical stress in interconnects has been modeled under the assumption that the overall structure after final process is in zero stress state at a presumed temperature, i.e. stress-free. Although this method is simple and often adequate to most needs, it does not provide adequate understanding of the stress evolution during the process. [4-6] For example, the fabrication of a simple M1-V1-M2 Cu BEoL structure requires multiple deposition processes including etch, CVD, Cu plating, CMP, etc. Each process step either adds or removes certain materials at a specific process temperature, and the stress state in the material will be affected by each step. Therefore, it is desirable to develop a process-oriented modeling approach, which takes into account of the effect of process changes on the stress evolution in all of the materials. [2] In order to better understand the stress evolution during the process, researchers have developed process-oriented stress modeling techniques. Among these, Cifuentes and Shareef [1] developed a numerical technique using artificial nodes to simulate material inter
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