A 3D Soft-EHL Model for Simulating Feature-scale Defects in Advanced Node ICs
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A 3D Soft-EHL Model for Simulating Feature-scale Defects in Advanced Node ICs Jonatan A. Sierra-Suarez1 , Gagan Srivastava2 , C. Fred Higgs 1,2 1 Electrical and Computer Engineering Department 2 Mechanical Engineering Department Carnegie Mellon University, Pittsburgh, PA 15232, U.S.A. ABSTRACT A new multiphysics, multiscale framework is presented which is capable of capturing and predicting both wafer-scale and feature-scale defects. Through physics-based modeling, the empirical wear/Preston coefficient often found in popular feature scale models has been eliminated. Simulation results show the topography evolution of an actual metal 1 layout between two dies located in different positions on a wafer during the CMP process. INTRODUCTION Semiconductor manufacturing continues to advance into smaller nodes allowing improved performance in a smaller package. However, systematic defects caused by variation in the manufacturing process play a larger role in the yield of wafers due to the smaller size of the features. Chemical mechanical polishing (CMP) is a manufacturing process for the removal and planarization of overburden material on each of the layers on the wafer. CMP is most popular for its use in copper planarization (since copper cannot be easily etched), oxide planarization (which eases the photolithography process), and shallow trench isolation (which allows for dense packing of transistors). The study of CMP is critical due to its inherent effect on other manufacturing processes and the diversity of physical and chemical interactions. The ability to accurately model CMP would lead to higher yield, shorter process maturation times, and the use of virtual simulations to analyze its effects on custom designs and materials. To date, the prominent physics-based models in the literature have been focused on either wafer scale, die scale, or feature scale modeling. The main benefit of a complete physics-based model lies in the ability to vary parameters without needing to perform experiments to generate CMP test data in order to better fit empirical models. It is important to note that variation occurs across all the scales as shown in Fig. 1. Due to multi-scale variation caused by CMP, one cannot adequately model the feature scale without taking wafer scale information into consideration. Feature scale variation, such as that caused by layout patterns, will also have an effect on the wafer scale, however, as that change would be several orders of magnitude smaller, this effect is assumed to be negligible throughout this paper. Models in literature such as those by Seok et al., Noh et al., Tripathi et al., and Wang et al., [1-4] have attempted to address multi-scale modeling. However, none of these multi-scale models simultaneously address the fluid dynamics, contact mechanics, particle dynamics, wear mechanisms, alongside the integrated circuit layout design. In this paper, a preliminary framework is introduced which captures and couples the predominant physics at both the wafer and feature scale for the metal 1 lay
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