A 530 nA quiescent current low-dropout regulator with embedded reference for wake-up receivers
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December 2020, Vol. 63 229404:1–229404:3 https://doi.org/10.1007/s11432-019-2715-1
A 530 nA quiescent current low-dropout regulator with embedded reference for wake-up receivers Shaoquan GAO, Hanjun JIANG* , Fule LI & Zhihua WANG Institute of Microelectronics, Tsinghua University, Beijing 100084, China Received 27 July 2019/Revised 12 September 2019/Accepted 25 November 2019/Published online 2 November 2020 Citation Gao S Q, Jiang H J, Li F L, et al. A 530 nA quiescent current low-dropout regulator with embedded reference for wake-up receivers. Sci China Inf Sci, 2020, 63(12): 229404, https://doi.org/10.1007/s11432-019-2715-1
Dear editor, Low power transceivers are essential in the wireless personal area network (WPAN) applications [1]. To reduce transceivers’ power in standby mode, wake-up receivers (WuRx’s) are now widely used in WPAN applications [2]. Those WuRx’s are always-on in the system and are usually powered by batteries. A compact low-dropout (LDO) voltage regulator with very small quiescent current is required to convert the battery voltage to the desired working voltage. Some recently reported low quiescent current LDOs are digital LDOs or the quasi-digital LDOs [3], but they exhibit very poor power supply rejection ratio (PSR) or large output ripple. For WuRx’s which are sensitive to the power supply noise/disturbance, an analog LDO is preferred. However, analog LDOs usually need a large decoupling capacitor, such as the analog LDO presented in [4] requires a 240 pF decoupling capacitor under the light load condition. Nevertheless, most LDOs need a separate voltage reference which requires extra current and chip area. The analog LDO with an embedded voltage reference in [5] consumes very low quiescent current (110 nA). However, it could only output a voltage around 1.2 V. In this study, a low quiescent current LDO with an embedded voltage reference is proposed. An error amplifier (EA) with asymmetrical input transistors is used for the closed-loop voltage regula-
tion. The EA’s input transistor pair is biased in the moderate inversion region, instead of the commonly used weak inversion region. The LDO output range is expanded without extra power consumption. The chip is designed and fabricated in a 180 nm CMOS process. The output voltage can be expanded to a given value between 1.3 V and 1.8 V with different settings of design parameters. The maximum quiescent current is only 530 nA, with a 1.6 V output and an input range of 1.8– 3.7 V. The load current range is 0–100 µA. Circuit architecture. The circuit architecture of the proposed LDO regulator is shown in Figure 1(a). The core circuitry consists of an EA with asymmetrical input transistors, a PMOS source follower buffer, a PMOS power passing transistor Mpass , a feedback network, and a Miller compensation network. There is no extra reference circuit required for this LDO. The auxiliary circuitry includes an adaptive biasing circuit for fast transient response. All the transistors used in this LDO are thick gate-oxide devices to tole
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