A High K Nanocomposite for High Density Chip-to-Package Interconnections
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A High K Nanocomposite for High Density Chip-to-Package Interconnections Taeyun Kim1, Jayesh Nath2, John Wilson2, Stephen Mick2, Paul D. Franzon2, Michael B. Steer2 and Angus I. Kingon1 1
Department of Materials Science and Engineering Department of Electrical and Computer Engineering North Carolina State University, Raleigh, NC 27695 2
ABSTRACT AC-coupled interconnects (ACCI) is a very exciting technology for achieving high-density chipto-package interconnects while simultaneously providing a simple, mechanically robust interface. The technology combines the stress-relieving ‘underfill’ layer with the dielectric medium for capacitive coupling. For good AC coupling, it is desirable for the underfill material to have a permittivity around 20 at operating frequencies. However, there is a lack of microwave frequency data for high permittivity ceramic-polymer composite systems in the literature. This paper describes the development and microwave frequency characterization of high K nanocomposite underfill. For composite thick film preparation, 200 nm BaTiO3 nano-sized powder and photosensitive epoxy were used. The thermal behavior of composites was evaluated by DSC (differential scanning calorimetry). Dielectric properties were evaluated as a function of ceramic loading and curing temperature. The microwave dielectric properties were measured from 45 MHz up to 26.5 GHz to extract the capacitance and quality factor of the capacitor over the frequencies of interest using floating plate capacitors and T-resonator CPW structures. The permittivity was found to be ~ 18 up to 14 GHz and the total Q factor of the capacitors was found to be 2 at 26.5 GHz for BaTiO3 (30 vol%)-epoxy composite. Dielectric loss was found to be 0.3 at 3 GHz, which would satisfactorily allow signaling well into the muti-gigabits range. The high K nanocomposite shows higher permittivity compared to materials currently used (air, K=1 or SiO2, K~3.9) in capacitively coupled interconnects for chip-topackage communications.
INTRODUCTION Increasing chip functionality demands a high density interconnect technology. One of the most commonly used interconnect technologies uses a direct, contacting path for every input/output connection. This limits achievable connect density in pin and ball grid arrays, and thermal mismatch stresses create rework and compliance problems in very high-density solder bump arrays. AC-coupled interconnects is a very promising technology for achieving high-density interconnects while simultaneously providing a simple mechanical interface [1,2]. In this technology buried solder bumps enable DC power and ground connections, and capacitors spaced across the same surface serves as the capacitively coupled interconnect for high frequency signals (figure 1). Most implementations of the AC-coupled interconnect concept requires that the chip and the substrate be brought into very close proximity (1~2 µm) to achieve the required capacitance for effective coupling due to the limited permittivity of dielectrics used (air, K=1 or SiO
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