A Novel Nanotube-on-Insulator (NOI) Approach toward Single-Walled Carbon Nanotube Devices
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0938-N07-10
A Novel Nanotube-on-Insulator (NOI) Approach toward Single-Walled Carbon Nanotube Devices Xiaolei Liu, Song Han, Daihua Zhang, Koungmin Ryu, and Chongwu Zhou Department of Electrical Engineering - Electrophysics, University of Southern California, Los Angeles, CA, 90007 ABSTRACT We present a novel nanotube-on-insulator (NOI) approach to produce nanotube devices. Based on the aligned nanotube arrays, we demonstrated registration-free fabrication of both topgated and polymer-electrolyte-gated field-effect transistors. In addition, we have developed a way to transfer these nanotube arrays to flexible substrates. Our approach has great potential for high-density, large-scale integrated systems based on nanotubes for both micro- and flexible electronics. INTRODUCTION Since discovered by Ijima in early 1990s [1], single-walled carbon nanotubes have become attractive new materials [2]. Beginning from 1998 when the first single-walled carbon nanotube field effect transistor (CNTFET) was built [3], great progress has been made to understand the transistor operation [4] and to improve the performance [5-8]. Early approaches toward fabricating CNTFETs include dispersing nanotubes onto pre-fabricated electrodes, or locating the nanotubes using various microscopes and then patterning the electrodes [3]. Alternatively, a chemical vapor deposition (CVD) technique has been developed by Dai et al. to grow nanotubes off patterned catalyst islands [9]. However, nanotube transistors made in the past are usually constructed atop Si/SiO2 substrates, with having rather large parasitic capacitance between the bonding pads and the underlying silicon substrate. Here, we present a high-yield, registration-free nanotube-on-insulator (NOI) approach based on aligned single-walled carbon nanotubes grown on a-plane sapphire substrates [10]. One distinct advantage of this NOI approach is that patterning of the source and drain electrodes is a registration-free process, as the aligned nanotubes are all over the sapphire substrate. In addition, this approach is in close analogy to the industry-adopted silicon-on-insulator (SOI) [11] or silicon-on-sapphire (SOS) approach, and they share one common feature of possessing minimized parasitic capacitance.
Figure 1. Schematics of (a) a silicon-on-insulator logic gate and (b) a nanotube-on-insulator logic. The insets are photographs of an SOI wafer and an NOI wafer, respectively.
Schematic diagrams of logic gates based on SOI and NOI techniques are shown in Figure 1 to illustrate the similarity. The simple SOI circuit shown in Fig. 1(a) can be fabricated by defining transistors at the desired locations, removing silicon from unwanted areas, and then patterning the interconnects. One characteristics of this SOI approach is that the electrodes of a SOI transistor reside atop the underlying silicon oxide instead of n- or p-well in traditional silicon devices leading to substantially smaller parasitic capacitance. Like SOI, we can fabricate NOI transistors shown in Fig 1(b) at any desired locati
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