A CMOS Compatible Carbon Nanotube Growth Approach
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A CMOS Compatible Carbon Nanotube Growth Approach Daire Cott1, Masahito Sugiura2, Nicolo Chiodarelli1,3,Kai Arstila 1, Philipe M. Vereecken 1,4, Bart Vereecke1, Sven Van Elshocht1 , and Stefan De Gendt1,5; 1 IMEC, 75 Kapeldreef, Leuven, Belgium 2 Tokyo Electron Ltd., Technology Development Center, 650 Mitsuzawa, Hosaka-cho, Nirasaki, Yamanashi 407-0192, Japan 3 Electrical Engineering, Katholieke Universiteit Leuven, Leuven, Belgium; 4 Center for Surface Chemistry and Catalysis, Katholieke Universiteit Leuven, Leuven, Belgium; 5 Department.of Chemistry, Katholieke Universiteit Leuven, Leuven, Belgium. ABSTRACT In future technology nodes, 22nm and below, carbon nanotubes (CNTs) may provide a viable alternative to Cu as an interconnect material. CNTs exhibit a current carrying capacity (up 9 to 10 A/cm2), whilst also providing a significantly higher thermal conductivity (SWCNT ~ 5000 WmK) over Copper (106 A/cm2 and ~400WmK). However, exploiting such properties of CNTs in small vias is a challenging endeavor. In reality, to outperform Cu in terms of a reduction in via resistance alone, densities in the order of 1013 CNTs/cm2 are required. At present, conventional thermal CVD of carbon nanotubes is carried out at temperatures far in excess of CMOS temperature limits (400 °C). Furthermore, high density CNT bundles are most commonly grown on insulating supports such as Al2O3 and SiO2 as they can effectively stabilize metallic nanoparticles at elevated temperatures but this limits their application in electronic devices. To circumvent these obstacles we employ a remote microwave plasma to grow high density CNTs at a temperature of 400 °C on conductive underlayers such as TiN. We identify some critical factors important for high-quality CNTs at low temperatures such as control over the catalyst to underlayer interaction and plasma growth environment while presenting a fully CMOS compatible carbon nanotube synthesis approach INTRODUCTION The electronic properties, conducting/semiconducting of carbon nanotubes (CNTs) are determined by their molecular structure in turn determining tube diameter, as a result each single walled CNT can be considered as a macromolecule with distinct chirality. For applications such as high volume field effect transistors (FET) fabrication strict control over their semiconducting properties is a prerequisite. Thus, for transistors, CNT synthesis can be considered as selective chiral molecular synthesis and at present the synthesis of one individual chiral controlled entity by CVD is a challenge yet to be realized. In the near future a more attainable goal for CNTs in microelectronics may be their use for interconnections as they could provide a viable replacement to Cu and W at sub 22nm dimensions. Here the chirality effect can be somewhat overlooked and the metallic nature [1], density (number of CNTs/cm2) [2], and synthesis compatibility with current CMOS processing become the critical factors [3]. For carbon nanotubes as on-chip vertical interconnections one integration target is at the metal co
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