A Predictive Model for Controlling Wafer Level Polish Rate Uniformity in Oxide CMP
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A Predictive Model for Controlling Wafer Level Polish Rate Uniformity in Oxide CMP Tushar P. Merchant1, Leonard J. Borucki1,2, A. Scott Lawing1,3, Suman K. Banerjee1, and John N. Zabasajja1 1 Technology Solutions, Freescale Semiconductor Inc., MD: EL722, Tempe, AZ-85284, U.S.A. 2 Intelligent Planar, 3831 E. Ivy St., Mesa, AZ-85205, U.S.A. 3 Rohm and Haas Electronic Materials, 3804 E. Watkins St., Phoenix, AZ-85034, U.S.A. ABSTRACT A stress based engineering model has been developed that predicts the removal rate profile across the wafer as a function of the principal and shear stresses on the wafer. The model reproduces the form of the radial variation in polish rate that is seen without back side air for the current set of consumable conditions and the changes in the polish rate profile that occur when back side air pressure is used on an IPEC-472 tool. The model which is GUI based and can be run in the fab, returns the optimum recipe setting to maximize polish rate uniformity based on the current tool performance. Implementing this model in production resulted in a 50% improvement in within wafer uniformity statistics. INTRODUCTION Removal rate uniformity is a key parameter in the control of CMP process performance. Thickness variation imposed by CMP can have a detrimental effect on wafer yield [1,2] especially as the number of polish steps in a typical process flow increases and this variation is compounded at later levels. CMP naturally introduces radial film thickness variation due to the radial non-uniformity of removal rate on the wafer and generally it is possible only to minimize and not totally eliminate this effect. Thickness or removal rate can also drift with time due to a number of factors including incoming film thickness variation and changes in consumable properties either lot-to-lot or as a function of age. The goal here was to develop a modeling tool to understand and account for the inherent variation in CMP removal rates across the wafer. The removal rate profile observed in the polishing SiO2 with a silica based slurry on a 200 mm wafer is typified by a relatively flat region in the center of the wafer, a local maxima between about 70 – 90 mm radius, a local minima within a few mm of the wafer edge and a sharp increase in removal rate near the wafer edge. While the exact positions of the profile peaks depend on the design of the wafer carrier such as the one for the IPEC-472 illustrated in Figure 1 (a), the shape is similar over multiple CMP platforms. A typical polish rate profile for the IPEC472 platform is illustrated in Figure 1 (b). Many attempts have been made to explain the radial dependence of the removal rate profile in CMP. The distribution of Von Mises stress as a function of wafer radius [3,4] shows good qualitative agreement with observed removal rate profiles and especially in matching the radial location of polish rate maxima and minima, but quantitative rate predictions are disconnected with experiment. Recently, Ng et al. [5] have shown that in the absence of wafer bend
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