The Development of a Direct-Polish Process for STI CMP
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The Development of a Direct-Polish Process for STI CMP Antonella Martin1, Giulia Spinolo1, Sonia Morin1, Maurizio Bacchetta1, Francesca Frigerio1, Benjamin A. Bonner2, Peter McKeever2, Maurizio Tremolada2, Anand Iyer2 1 ST Microelectronics, 20041 Agrate Brianza, Via C. Olivetti, 2 Italy 2 Applied Materials, 3111 Coronado Drive, Santa Clara, CA 95054, USA ABSTRACT The development of a direct polish process for STI CMP on 200mm wafers using highselectivity slurry (HSS) has been achieved for production of 0.13µm technology microelectronic devices. The new process has improved on-wafer performance compared to standard STI CMP processes. The step height range across the wafer was decreased by 84%, planarity Cpk values (silicon nitride thickness and step-height uniformity) were increased by >25%, leakage current statistics were superior, and the cost of ownership was lowered by 78%. Cross-sectional SEMs both after direct polish CMP and after removal of the silicon nitride show improved planarity. INTRODUCTION The move to faster and smaller semiconductor devices has led to unprecedented planarity requirements and the shrinking line widths have rendered the formation of transistors using conventional local oxidation of silicon (LOCOS) techniques obsolete [1]. A robust Shallow Trench Isolation (STI) process is necessary to meet the stringent requirements of sub 0.25µm devices. The most important advantage STI offers is that it significantly reduces the area required to isolate transistors thus enabling a higher packing density. STI also provides the high degree of planarity that is essential to meet stringent photolithography requirements [2-3]. Currently STI structures are formed by etching into a silicon wafer that contains a layer of silicon nitride (SiN) then filling the resulting trenches with a silicon oxide film. A chemical mechanical polishing (CMP) step is then used to planarize the oxide after trench fill, finally stopping on the SiN layer. Conventional STI CMP is unable to effectively planarize structures with wide pattern densities that are typically present in most die layouts [3]. Typically, a reverse mask process is used whereby the oxide is etched away from the large and high-density active areas to reduce the degree of non-planarity. However, this process is complicated and involves additional photolithography, etching, and cleaning steps [2-7]. The ability to planarize using only CMP, termed direct-polish STI CMP, would eliminate all of the aforementioned steps thereby reducing manufacturing complexity and cost. Requirements for direct-polish STI CMP processes include minimal within die (WID) oxide and SiN ranges, reduced SiN loss and oxide dishing, and excellent uniformity, both within wafer (WIW) and wafer-to-wafer (WTW) [3,8]. All of these are required to give a nominal, consistent, and repeatable step height (silicon to oxide) after the SiN has been removed. In addition to enabling good planarity, the process must also exhibit excellent defect performance. Any direct polish process must be deve
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