A Study of the Factors Which Determine the Modulation Speed of a Shallow PN Junction Porous Silicon Led
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ABSTRACT The effect of the chemical thinning of the porous silicon structure on the speed and efficiency of electroluminescent devices, produced by the anodisation of a pn junction in bulk silicon is investigated. Thinning of the silicon wires results in an increase in the efficiency but at the expense of a reduction in operating speed. It is demonstrated that the operating speed is limited by the photoluminescence lifetime for small signal excitation. However, for large signals, the electroluminescence can be turned off more than 5 times faster than the photoluminescence lifetime, indicating that this need not necessarily limit device operating speed. INTRODUCTION The demonstration [1] that it is possible to obtain efficient visible photoluminescence (PL) at room temperature from porous siliccon (PS) opened up the possibility of all silicon optoelectronics. Applications envisaged include PS light emitting devices (LEDs) for optical interconnection and emissive displays integrated with silicon circuitry. For optical interconnection, it is important to be able to modulate the electroluminescence at frequencies greater than 100 MHz and with an external power efficiency greater than 1%. ]EL efficiencies greater than 0.1% have been reported in PS LEDs, produced by porosifying pn junctions made in bulk silicon, under both CW operation [2] and pulsed operation [3]. Several groups have made measurements which indicate that modulation of PS LEDs at frequencies greater than 1 MHz may be possible, albeit from devices with lower than 0.1% power efficiency [4-6]. The maximum -3dB frequency reported for small signal modulation of the EL of a PS LED is greater than 1 MHz [4]. For excitation of the EL with a square pulse, rise times as small as 100 nsec have been reported by several groups [4-6]. Fall times as short as 30 nanoseconds have also been reported [6]. In this paper, we investigate the fictors limiting the modulation speed of PS devices which are similar to those we previously reported [2] to have a CW external power efficiency of 0.1%. The fabrication of this device has been described in detail [7]. In summary, the device has an indium tin oxide (ITO) contact (100 nm thick) on top of a porous silicon region of thickness -400 nm on an n-type substrate of resistivity in the ramge 10-20 Qcm. The PS region is formed by the anodisation of a pn junction prepared by implanting the substrate with boron at an energy of 35 keV to a dose of 10 16 cm 2. The light assisted anodisation is performed at a current density of 3 mAcm- in 40 wt% aqueous hydrofluoric acid for four minutes. During anodisation, the silicon skeleton formed by the electrochemical process is also reduced in size by photochemical etching by the electrolyte. Here, we examine two devices which are similar to that reported in reference [2]. Device A is chosen to have a shallower junction than the prior more efficient device [2] and thereby to reduce the chemical etching component. This is achieved by reducing both the implantation energy and the anodisation time. T
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