Challenges of Ultra Low-k Dielectric Measurement and Plasma Damage Assessment
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Challenges of Ultra Low-k Dielectric Measurement and Plasma Damage Assessment Thomas Abell1, Jeffrey Lee2, and Mansour Moinpour3 1 Technology and Manufacturing Group, Intel Corp., 2200 Mission College Blvd. SC1-05, Santa Clara, CA, 95052-8119 2 Affiliate Researcher, Intel at IMEC, 75 Kapeldreef, Leuven, Belgium 3 Fab Materials Group, Intel Corp., 2200 Mission College Blvd, Santa Clara, CA, 95052-8119
ABSTRACT The implementation of porous low-k and ultra-low k dielectrics to reduce RC delay in integrated circuit interconnect wiring has been fraught with numerous challenges. The obvious challenges of materials design and preservation of the desired electrical and mechanical properties upon subsequent processing have been significant. The vulnerability of these films to damage from fast ion and radiation damage will be discussed in the context of post-deposition processing (including low-k cure and plasma processing damage). This paper attempts to review the challenges associated with destructive and non-destructive measurement of low k dielectric films with respect to underlying physical principles of the metrology. Metrology techniques, assumed to be non-destructive based on experience with dense silicon dioxide, will be discussed with regards to newer and more fragile low-k dielectric films. INTRODUCTION Low k dielectric films have been pursued for integrated circuit manufacturing to reduce the capacitive contribution to RC signal delay that threatens to limit device performance [1]. The first of many challenges related to the pursuit of low-k dielectrics has been the design of materials that can be deposited as uniform thin films with k-values well below that of dense CVD-deposited silicon dioxide. CVD processes utilizing carbon containing precursors have been one route that has produced methyl-group induced microporous films with interlinked Si-O-Si structures. These films have a relatively random molecular structure but have proven to be robust enough for integration into semiconductor device fabrication. Thin films produced from spin-on solutions have also been extensively pursued using a number of different materials systems. Organo-silicates have been spin-deposited and cured to produce sequioxane cage-like structures that can result in highly porous and low k-value films. Porosity of these films has also been modified by various schemes involving the post-deposition removal of porogens. Polymer material systems have also been extensively investigated due to the potential for very low inherent k-values. Spin-on polymers with and without porogen-removal schemes have been examined. But most have suffered from mechanical and thermal coefficient of expansion issues leading to their low utilization in semiconductor device manufacturing.
All of these material systems, regardless of deposition technique, must be patterned for Cu-damascene process flows using lithographic techniques and plasma-based etch systems (creating trenches and vias for subsequent fill by electroplated Cu). Implementation of all
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