Characterization of Low Temperature Polysilicon TFTs with Self-Aligned Graded LDD Structure
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Characterization of Low Temperature Polysilicon TFTs with Self-Aligned Graded LDD Structure Ching-Wei Lin, Li-Jing Cheng, Yin-Lung Lu, and Huang-Chung Cheng Institute of Electronics, National Chiao Tung University, Hsinchu, 300, Taiwan, R.O.C. ABSTRACT A simple process sequence for fabrication of low temperature polysilicon (LTPS) TFTs with self-aligned graded LDD structure was demonstrated. The graded LDD structure was self-aligned by side-etch of Al under the photo-resist followed by excimer laser irradiation for dopant activation and laterally diffusion. The graded LDD polysilicon TFTs were suitable for high-speed operation and active matrix switches applications because they possessed low-leakage-current characteristic without sacrificing driving capability significantly and increasing overlap capacitance. The leakage current of graded LDD polysilicon TFTs at Vd = 5V and Vg = -10V could attain to below 1pA/µm without any hygrogenation process, when proper LDD length and laser activation process were applied. The on/off current ratios of these devices were also above 108. Furthermore, due to graded dopant distribution in LDD regions, the drain electric field could be reduced further, and as a result, graded LDD polysilicon TFTs provided high reliability for high voltage operation. INTRODUCTION Low temperature polysilicon (LTPS) TFTs have been widely studied for active matrix liquid crystal displays [1]. In general, the mobility of polysilicon TFTs is two-order higher than that of amorphous TFTs, so that peripheral driving circuits can be integrated with active matrix array on the same substrate. As a result, high-definition displays with low cost can be achieved by LTPS TFTs technology. Recently, the concept of system-on-panel has further been proposed in order to make displays more versatile [2]. In the system-on-panel applications, TFTs must possess high performance and high reliability while retain low fabrication cost. Conventionally, polysilicon TFTs with LDD or offset structure were used to suppress leakage current and enhance device reliability. Additional processes, such as lithography and ion doping, usually must be performed in order to form this kind of device structure, which makes the fabrication cost increase. Besides, the misalignments occurred in lithography process also cause the asymmetric electrical characteristics in these devices [3]. Although the LDD structure could suppress leakage current and enhance device reliability, unfortunately, it might degrade the device driving capability due to large series resistance existing in the LDD regions [4]. D12.7.1
In this paper, we used side-etch of gate electrode combined with multi-shots excimer laser irradiation for dopant activation to form the self-aligned graded LDD structure. The electrical characteristics and reliability of TFTs with different lengths of side-etch (defined as graded LDD lengths) and shot numbers in laser activation were also examined. It is shown that with proper process conditions, the leakage current of TFTs with graded LDD
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