Code conversion in compositional microprogram control units
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CODE CONVERSION IN COMPOSITIONAL MICROPROGRAM CONTROL UNITS A. A. Barkalova and L. A. Titarenkob
UDC 004.383.3
Abstract. The joint use of structural decomposition and code conversion is proposed. The method is oriented to reducing the hardware in compositional microprogram control units. This reduction is due to the decrease in the number of arguments for irregular functions and in the number of the functions themseves. Embedded memory blocks are used to implement regular functions. Design methods and an example are discussed. Experimental results are given. Keywords: compositional microprogram control unit, FPLD, structural decomposition, optimization INTRODUCTION Methods of hardware optimization in control unit (CU) circuits depend both on the characteristics of the control algorithm and on the parameters of hardware components [1]. Functional decomposition is an optimization method for CU circuits implemented on field programmable logic devices (FPLD) such as field programmable gate arrays (FPGA) [2, 3]. The reason is that such FPLDs are based on LUT (look-up table) logic elements (LEs) [4, 5]. If the control algorithm is linear, it may be interpreted using the model of compositional microprogram control unit (CMCU) [6]. In the CMCU, the system of microoperations is implemented on read-only memory (ROM). To this end, embedded memory blocks (EMBs) of modern FPLDs such as FPGA [7, 8] can be efficiently used. We will use the notation FPLD for FPGA, LE for LUT, and EMB for built-in memory block. To reduce the number of LEs in a CU circuit, it is necessary to reduce both the number of arguments in the functions and the number of functions dependent on logical conditions. To solve the first problem, we propose to convert input codes of operator linear circuits (OLCs) of the control algorithm to codes of classes of pseudoequivalent OLCs. To solve the second problem, OLC input codes are proposed to be converted into the addresses of the corresponding microcommands. The control algorithm is represented as a flow chart (FC) [1], and a CMCU model with common memory [6] is used to define the CU. Note that the proposed methods can be adapted to other forms of algorithm representation and other CMCU models. CMCU MODEL WITH COMMON MEMORY Let a control algorithm for a digital system be presented as an FC G, which is characterized by the sets of nodes B = E1 È E 2 È {b0 , bE } and of arcs E connecting these nodes; E1 is the set of operator nodes containing sets of microoperations from the set of microoperations Y = { y1 , K , y N } ; E 2 is the set of conditional nodes containing elements of the set of logical conditions (LCs) X = {x1 , K , x L } ; b0 is the initial node; and bE is the final node of the FC G. Let us introduce some definitions [6]. Definition 1. An operator linear circuit of the FC G is a finite sequence of operator nodes a g = < bg 1 , K , bg Fg > such that for any pair of its neighboring nodes there exists an arc < bgi , bgi + 1 > Î E, where i = 1, K , Fg -1 . a
Donetsk National Technical University, Donetsk
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