Control of Si-SiO 2 Interface Properties in MOS Devices Prepared by Plasma-Assisted and Rapid Thermal Processes
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Si,Ge source-drain contacts means that any necessary annealing of the Si-SiO 2 heterostructures at -900*C may eventually have to be accomplished during, or immediately after their formation, and not during the downstream steps which may no longer require processing temperatures as high as 900*C. This has prompted the exploration of processing sequences for deposited dielectrics that separately control (i) interface and (i) bulk dielectric formation, but also include (iii) the rapid thermal annealing, RTA, step(s) required to promote device-quality performance and reliability. To illustrate problems associated with concurrent interface creation and film growth during a single-step oxide deposition process, we describe a low-temperature plasma-assisted process wherein cleaning and passivation of the Si surface by exposure to plasma-generated H-atoms are performed prior to a plasma-assisted oxide deposition [4,7-91. In this approach, the Si-SiC 2 interface is formed by subcutaneous oxidation that occurs concurrently with the initial stages of oxide deposition [8,9]. This type of uncontrollableinterface formation severely restricts process latitude, as well as promoting marginal electrical performance and reliability. We then describe an improved approach in which the Si-SiO 2 interface is formed during a 300'C pre-deposition plasma-
assisted oxidation [4]. This in-situ process removes residual C-contamination, and produces -0.50.6 nm of oxide, which preserves the electrical quality of the Si-SiC 2 interface during subsequent downstream processes. We have used two deposition processes for MOS device fabrication: (i) one in which oxide deposition is by remote plasma-enhanced CVD at 300 0 C [6,10], and (ii) a second in which oxide deposition is by rapid thermal CVD at 800'C [11,12]. In each of these methods, it was necessary to include mid- and/or end-of-process RTAs to optimize the electrical properties of Si-SiO2 interfaces and FET devices, and to ensure the reliability of FET devices. An empirical understanding of the physics and chemistry underlying important aspects of SiSiO2 interface formation that impact on the interfacial electrical properties has evolved in parallel with the evolution of increased process and processing chamber functionality. Chamber designs have focused on process flexibility, defined here as the ability to (i) perform more than one process step, e.g., oxidation and deposition, and/or (ii) use more than one processing technique, e.g., remote PECVD, RTCVD and RTA, in the same chamber. In this paper, we track improvements in the electrical properties of Si-SiC 2 interfaces with deposited oxides for three different approaches to singe-wafer, integrated-processing which have employed (i) single-process / single-function chambers [8], (ii) single-process / dual-function chambers [4,6], and most recently, (iii) multiprocess / multi-function chambers [11,12]. The chambers designated as (i) and (ii) have employed low-temperature, -300 0 C, plasma-assisted processes, whilst the one labeled (iii) has c
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