Defect States in Excimer-Laser Crystallized Single-Grain TFTs Studied with Isothermal Charge Deep-level Transient Spectr
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0910-A19-02
Defect States in Excimer-Laser Crystallized Single-Grain TFTs Studied with Isothermal Charge Deep-level Transient Spectroscopy V. Nadazdy1, V. Rana2, R. Ishihara2, S. Lanyi1, R. Durny3, J.W. Metselaar2, and C.I.M. Beenakker2 1 Institute of Physics Slovak Academy of Sciences, Dubravska cesta 9, Bratislava, Slovak Republic, 845 11, Slovakia 2 DIMES, Delft University of Technology, DELFT, N2628 CT, Netherlands 3 Department of Physics, Slovak University of Technology, Bratislava, 812 19, Slovakia ABSTRACT Defect states were quantitatively evaluated in single-grain (SG) Si thin-film transistors (TFTs), prepared by micro-Czochralski (grain filter) process with excimer-laser crystallization, by means of isothermal charge deep-level transient spectroscopy with a high sensitive charge/voltage converter. Its sensitivity reaches 10-16 C and it operates in the range of 2 µs − 10 ms. Measurements were performed on the SG-Si TFTs with various energy densities of laser crystallization, various channel areas, and positions in the grain. Our results indicate a direct correlation of fabrication parameters, parameters of the TFT determined from its transfer characteristics, and parameters of defect states (energy position in the band gap, concentration) induced by coincidence site lattice boundaries inside the location-controlled grains and by defects in the grain filter. INTRODUCTION Excimer-laser induced crystallization of a-Si film enables poly-Si film based thin film transistor (TFT) formation on a glass or plastic substrate at temperatures below 350 oC. Novel technology of location-controlled single-grain (SG) Si TFTs referred to as microCzochralski (grain filter) process [1] allows creation of crystalline Si (c-Si) islands with an area of 6x6 µm2 located at predetermined positions and formation of the TFT inside a grain. This process leads to much higher electron mobility (450 cm2/Vs) [2] than for standard lasercrystallized poly-Si TFTs (around 100 cm2/Vs). Recently, the effect of remaining defects inside the location-controlled grains on the electrical performance of single-grain (SG) Si TFTs was studied [2]. From electron backscattering diffraction analysis, it was found that most of the defects inside the location-controlled grains are coincidence site lattice (CSL) boundaries and the performance is dependent on the position of boundary defects in the TFT channel. On a macroscopic scale, deep-level transient spectroscopy (DLTS) has become a well established method for characterization of defect states in semiconductors and their interfaces with oxides. To benefit from its advantages in the fabrication process of small size electronics and in the developing nanotechnology research the absolute sensitivity of the DLTS setup needs to be improved. A possible way to solve this problem for field-effect transistors (FETs) is using current [5] or conductance [6] versions of DLTS. These concepts profit from the indirect detection of charge released from traps via measured drain-current and/or the amplification effect of t
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