Study of Back-Channel Defect States on Bottom-Gate IGZO TFTs Using Capacitance-Voltage Analysis
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Study of Back-Channel Defect States on Bottom-Gate IGZO TFTs Using Capacitance-Voltage Analysis T. Mudgal1, N. Walsh1, N. Edwards1, R.G. Manley2 and K.D. Hirschman1 1
Electrical & Microelectronic Engineering Department Rochester Institute of Technology, Rochester, New York, 14623, USA 2
Corning Incorporated, Science and Technology Division Corning, New York, 14870, USA ABSTRACT This work investigates the quality of back-channel passivation applied to sputterdeposited IGZO bottom-gate TFTs. Passivation materials investigated were alumina, silicon dioxide, and B-staged bisbenzocyclobutene-based (BCB) resins. Sputtered quartz and PECVD (TEOS) SiO2 rendered the IGZO material highly conductive (ρ < 0.01 Ω·cm), with subsequent annealing in oxidizing ambient unable to restore a high-resistivity state. Appropriate channel resistivity was restored on devices passivated with electron-beam evaporated alumina and spincoated BCB when followed by annealing in air. Alumina passivated devices demonstrated improved stability; however slight distortions in measured I-V and C-V characteristics were observed. TCAD simulation was used to develop an IGZO material/device model, with results indicating the significant presence of oxygen-vacancy (OV) interface traps and negative fixed charge remaining at the back-channel. INTRODUCTION The understanding of the nature and distribution of defect states in indium-gallium-zinc oxide (IGZO) is important to address instability [1]. Back-channel passivation is required for process integration and to ensure consistent electrical behavior over time. Unfortunately the passivation process may compromise the thin-film transistor (TFT) performance due to subjecting the IGZO back channel to exposure of some combination of vacuum, plasma, and elevated temperature. Capacitance-voltage (C-V) analysis in conjunction with current-voltage (I-V) measurements can help in identifying these defects and developing a comprehensive material and device model. However for thin-film electronics performing C-V analysis is a 2D problem. Measuring C-V characteristics on a TFT is possible, however the effective capacitance of a TFT is extremely small (~1 pF), and measurement noise makes the interpretation of defect states exceedingly difficult. While researchers have addressed this by using sophisticated measurement systems [2], the approach in this work is to perform C-V analysis on interdigitated capacitors (IDC) designed to provide a much larger area while still representing the TFT channel region. Both C-V and I-V datasets were used to develop a comprehensive IGZO material/device model.
Downloaded from https:/www.cambridge.org/core. Monash University, on 23 Apr 2017 at 08:27:23, subject to the Cambridge Core terms of use, available at https:/www.cambridge.org/core/terms. https://doi.org/10.1557/opl.2015.173
EXPERIMENT Bottom-gate top-contact TFTs and IDCs were fabricated using RF sputtered IGZO (1:1:1:4); the details of fabrication are described elsewhere [3]. Various passivation material and anneal treatments were
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