Diagnosis of Multiple Stuck-at Faults Using Fault Element Graph with Reduced Power
As the manufacturing processes become more and more advanced as per Moore’s law, precise control of silicon process is becoming more and more challenging. This increases the probability of defects and has brought a necessity for testing to ensure fault-fr
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Abstract. As the manufacturing processes become more and more advanced as per Moore’s law, precise control of silicon process is becoming more and more challenging. This increases the probability of defects and has brought a necessity for testing to ensure fault-free products, making the testing of a chip more complex causing testing challenges. With large number of transistors, in multiples of thousands being integrated in one chip, multiple stuck-at faults may exist, because of which fault masking and reinforcing effects may come into effect. This may lead to the failure of approaches like Single Location at a Time (SLAT) and restricted single sensitized paths. To counter this, the notion of fault element is used to take into account multiple fault models and use a fault element graph (FEG) to consider fault masking and reinforcing effects among multiple faults. To identify these faults, appropriate test patterns need to be generated that would carry the effect of the fault to the primary output. The test patterns are chosen such that switching power is made to be a minimum. Keywords: Fault Fault element graph Fault location Test pattern Failing pattern Switching power
1 Introduction Fault diagnosis plays a very important part in the industry, since after each fabrication level there are many irregularities which could occur and with every level, cost of testing increases. A fault can be diagnosed either using Physical failure analysis (PFA) or the software based fault diagnosis tools that can provide definite candidate faults. Single faults have been well studied in the literature [1]. However when multiple faults exist, a fault model fails to accurately locate the actual faults [2]. Results of [3], which use SLAT patterns to detect faults show that almost 41 % of the faults are not diagnosed accurately using single stuck-at fault models. Previous work on multiple combinational logic faults show that faults can be grouped into two main categories: Diagnostic test-pattern based [4] and Manufacturing test-pattern based [5–15]. The first category deals with finding failing patterns and then further diagnostic test patterns, which distinguishes candidate faults. This process is repeated after each step of identifying the probable candidate locations. Though this method may give high diagnosis quality, it is a costly method to run the test many © Springer Nature Singapore Pte Ltd. 2016 P. Mueller et al. (Eds.): SSCC 2016, CCIS 625, pp. 414–426, 2016. DOI: 10.1007/978-981-10-2738-3_36
Diagnosis of Multiple Stuck-at Faults
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number of times. The second category does not generate diagnostic patterns but compares failing responses under test patterns with the failing responses of potential faults and then arrives upon different candidate locations. In this paper, a manufacturing test pattern based diagnosis method is proposed which also considers the fault masking and reinforcing effect using fault element graphs (FEG). Fault Masking is an occurrence, in which one defect prevents the detection of another. F
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