Diffusion Behavior of B-, As- and Sb-Dopants in Thin Epitaxial Layers
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ABSTRACT Advanced CVD- and MBE-epitaxy allows processing of very thin epitaxial layers with extremely steep dopant gradients. As steep dopant profiles are very sensitive to temperature treatments, the impact of thermal processing from 800'C to 1000°C on the dopant redistribution in epitaxial layers was investigated.
INTRODUCTION Modem microelectronics is based on MOS transistor technology. The impressive progress of the MOS transistor performance became possible by scaling of the device structure size. Basic performance parameters of MOS transistors, such as transconductance and cut-off frequency, increase following a power-law as a function of the channel length. It has been shown that MOS transistors can be scaled well into the sub-100 nm range
[1-2], but the decrease of the structure size below the quarter-micron dimension is accompanied by sharply increasing costs for the lithography. Therefore, alternative approaches are of interest to process very short channel lengths with standard lithographic equipment. This can be realized by a vertical design of the MOS transistors [3]. The length of the channel region of this device type is determined by an epitaxial layer which can be deposited by Chemical Vapor Deposition (CVD) or Molecular Beam Epitaxy (MBE). As the epitaxial layer is deposited in the beginning of the process, the channel length of a vertical MOS transistor is defined very early in the process. This is different from the process sequence of conventional MOS transistors. The consequence is that the channel region of a vertical MOS transistor is exposed to subsequent thermal process steps, such as gate oxide growth. For maintaining well-defined dopant profiles of the channel region throughout the fabrication process, the impact of thermal process steps on the dopant profiles in epitaxial layers has to be known. Therefore, the shift of the dopant profiles processed by CVD- and MBE-epitaxy, respectively, was investigated as a function of the thermal treatment by experiments and by simulations.
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Mat. Res. Soc. Symp. Proc. Vol. 358 0 1995 Materials Research Society
FABRICATION OF TEST STRUCTURES For the deposition of the CVD-layers, we used a cold wall single wafer reactor with radiant heating. The growth was performed at a pressure of 2 to 10 Torr with a gas mixture of H2 , SiH 2 CI 2 and B2 H6 or AsH 3 for p-type and n-type doping, respectively. The wafer temperature was measured with a pyrometer directed towards the back side of the wafer. At a temperature of 900'C, growth rates of 50 nm/min for undoped and Boron doped layers were achieved, but only 6 nm/min for Arsenic doped layers. The MBE epitaxy was performed in an indigenous UHV system. The base pressure was 6.10-10 mbar rising to 2 -10-9 mbar during silicon evaporation. The growth rate of the epitaxial layers was chosen as 4.8 mn/min. The substrate temperature was monitored by pyrometry and was set to 470'C for the growth of the highly doped layers and to 700'C for the nominally intrinsic layers. The p-doping was achieved by boron evapora
