Digital Design and Implementation with Field Programmable Devices
This book is on digital system design for programmable devices, such as FPGAs, CPLDs, and PALs. A designer wanting to design with programmable devices must understand digital system design at the RT (Register Transfer) level, circuitry and programming of
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Digital Design and Implementation with Field Programmable Devices
Zainalabedin Navabi Northeastern University
KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW
CD-ROM available only in print edition eBook ISBN: 1-4020-8012-3 Print ISBN: 1-4020-8011-5
©2005 Springer Science + Business Media, Inc. Print ©2005 Kluwer Academic Publishers Boston All rights reserved No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America
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About the Author
Dr. Zainalabedin Navabi is an adjunct professor of electrical and computer engineering at Northeastern University. Dr. Navabi is the author of several textbooks and computer based trainings on VHDL, Verilog and related tools and environments. Dr. Navabi's involvement with hardware description languages begins in 1976, when he started the development of a register-transfer level simulator for one of the very first HDLs. In 1981 he completed the development of a synthesis tool that generated MOS layout from an RTL description. Since 1981, Dr. Navabi has been involved in the design, definition and implementation of Hardware Description Languages. He has written numerous papers on the application of HDLs in simulation, synthesis and test of digital systems. He started one of the first full HDL courses at Northeastern University in 1990. Since then he has conducted many short courses and tutorials on this subject in the United States and abroad. In addition to being a professor, he is also a consultant to CAE companies. Dr. Navabi received his M.S. and Ph.D. from the University of Arizona in 1978 and 1981, and his B.S. from the University of Texas at Austin in 1975. He is a senior member of IEEE, a member of IEEE Computer Society, member of ASEE, and ACM.
To my wife, Irma and my sons Arash and Arvand.
CONTENTS
Preface
1
PLD Based Design Design Flow 1.1 Design Entry 1.2 1.2.1 Discrete Logic 1.2.2 Pre-Designed Components 1.2.3 Configurable Parts 1.2.4 Generic Configurable Functions 1.2.5 Configurable Memories 1.2.6 HDL Entry Simulation 1.3 1.3.1 Pre-Synthesis Simulation 1.3.2 Post-Synthesis Simulation 1.3.3 Timing Analysis Compilation 1.4 1.4.1 Analysis 1.4.2 Generic Hardware Generation 1.4.3 Logic Optimization 1.4.4 Binding 1.4.5 Routing and Placement Device Programming 1.5 1.5.1 Configuration Elements 1.5.2 Programming Hardware Summary 1.6
xiv
3 3 4 5 5 6 6 6 7 8 8 10 11 12 13 13 13 13 14 14 14 15 16
viii
2
3
Digital Design and Implementation with Field Programmable Devices
Logic Design Concepts
17
Number Systems 2.1 2.1.1 Binary Numbers 2.1.2 Hexadecimal Numbers Binary Arithmetic 2.2 2.2.1 Signed Numbers 2.2.2 Binary Addition 2.2.3 Binary Subtraction 2.2.4 Two's Complement System 2.2.5 Overflow 2.3 Basic Gates 2.3.1 Logic Value System 2.3.2 Transistors
