Dynamics, Design, and Application of a Silicon-on-Insulator Technology Based Neuron
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MRS Advances © 2018 Materials Research Society DOI: 10.1557/adv.2018.490
Dynamics, Design, and Application of a Silicon-onInsulator Technology Based Neuron S. Dutta1, T. Chavan1, S. Shukla1, V. Kumar1, A. Shukla1, N. Mohapatra2 and U. Ganguly1
1
Indian Institute of Technology Bombay
2
Indian Institute of Technology Gandhinagar
Abstract:
Spiking Neural Networks propose to mimic nature’s way of recognizing patterns and making decisions in a fuzzy manner. To develop such networks in hardware, a highly manufacturable technology is required. We have proposed a silicon-based leaky integrate and fire (LIF) neuron, on a sufficiently matured 32 nm CMOS silicon-on-insulator (SOI) technology. The floating body effect of the partially depleted (PD) SOI transistor is used to store “holes” generated by impact ionization in the floating body, which performs the “integrate” function. Recombination or equivalent hole loss mimics the “leak” functions. The “hole” storage reduces the source barrier to increase the transistor current. Upon reaching a threshold current level, an external circuit records a “firing” event and resets the SOI MOSFET by draining all the stored holes. In terms of application, the neuron is able to show classification problems with reasonable accuracy. We looked at the effect of scaling experimentally. Channel length scaling reduces voltage for impact ionization and enables sharper impact ionization producing significant designability of the neuron. A circuit equivalence is also demonstrated to understand the dynamics qualitatively. Three distinct regimes are observed during integration based on different hole leakage mechanism.
INTRODUCTION Spiking Neural Networks (SNN) is an attempt to mimic brain’s way of recognizing patterns and making decisions in an unstructured way. The human brain consists of billions of neurons connected by trillions of synapses which makes this biological neural network an extremely complex system. To build such a network in hardware, two aspects need to be taken care of. First, the integration of these numerous neurons in hardware calls for a highly manufacturable technology. Second, it is a highly challenging task to match brain’s extreme energy efficiency. CMOS, being sufficiently matured technology, offers potential solutions [1][2][3] but could not compete with biology due to its large area and high power consumption. Some novel material based neurons (IMT[4], Phase Change Material [5], PCMO [6]) have also been proposed. These demonstrations are promising in terms of area and energy, but VLSI is a challenge due to CMOS
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incompatibility. Our group proposed a partially depleted SOI or PD-SOI MOSFET based electronic neuron by utilizing its intrinsic carrier dynamics [7]. The well-known floating body effect due to impact ionization (II) in a PD SOI neuron
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