Extended Lock Range Zero-Crossing Digital Phase-Locked Loop with Time Delay
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Extended Lock Range Zero-Crossing Digital Phase-Locked Loop with Time Delay Qassim Nasir Department of Electrical and Computer Engineering, College of Engineering, University of Sharjah, P.O. Box 27272, Sharjah, UAE Email: [email protected] Received 7 November 2004; Revised 21 May 2005; Recommended for Publication by Jonathon Chambers The input frequency limit of the conventional zero-crossing digital phase-locked loop (ZCDPLL) is due to the operating time of the digital circuitry inside the feedback loop. A solution that has been previously suggested is the introduction of a time delay in the feedback path of the loop to allow the digital circuits to complete their sample processing before the next sample is received. However, this added delay will limit the stable operation range and hence lock range of the loop. The objective of this work is to extend the lock range of ZCDPLL with time delay by using a chaos control. The tendency of the loop to diverge is measured and fed back as a form of linear stabilization. The lock range extension has been confirmed through the use of a bifurcation diagram, and Lyapunov exponent. Keywords and phrases: nonuniform sampling, digital phase locked loops, chaos control.
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INTRODUCTION
Digital phase locked loops (DPLLs) were introduced to minimize some of the problems associated with the analogue loops such as sensitivity to DC drift and the need for periodic adjustments [1, 2]. The most commonly used DPLL is the zero-crossing digital phase-locked loop (ZCDPLL). The ZCDPLL operation is based on nonuniform sampling techniques. The loop is simple to implement and easy to model. The ZCDPLL consists of a sampler that acts as phase detector, digital filter, and digital-controlled oscillator (DCO). In the ZCDPLL, there is a limit on the frequency of the incoming signal beyond which the loop ceases to function properly any longer. This limit is reached when the period of the incoming signal becomes equal to the total operating time of the digital circuits in the loop. One way to increase this upper limit of the input frequency is by the introduction of a time delay in the loop. In this case the sampling instances controlled by the DCO are determined by the sample of the input which was taken two sampling intervals earlier. Therefore, the upper limit of the operating frequency of the ZCDPLL can be increased. The introduction of the delay, however, will limit the loop stability range or the lock range of the loop as will be seen later. The objective of this work is to increase the stability and lock range of ZCDPLL with time delay by incorporatThis is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
ing a chaos control technique known as “time-delayed feedback stabilization.” The ZCDPLL has been shown to exhibit chaotic behaviour in the unstable region of operation [3]. Time-delayed feedback stabilization introduced by Pyragas co
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