Failure in Tungsten-Filled Via Structures
- PDF / 1,213,348 Bytes
- 6 Pages / 414.72 x 648 pts Page_size
- 18 Downloads / 206 Views
ABSTRACT Failure of the tungsten-filled via interconnect structure is modelled. Two mechanisms contributing to void growth are considered: relief of stress due to differential thermal expansion, and electromigration. A self-limiting void volume is predicted, resulting in a self-limiting resistance increase which is a function of structure geometry and the void morphology. The relative contributions of the two mechanisms change significantly as the temperature and current density are reduced from accelerated test conditions, affecting the extrapolation of test results to service conditions. Modified procedures for extrapolating lifetimes are discussed, as well as suggested process changes to improve reliability.
INTRODUCTION The multilevel metalization in most modern ULSI circuits uses interconnects made up of an Al-alloy layer sandwiched between refractory layers over and under, with tungstenfilled vias connecting one level of interconnect to another. Reliability is typically evaluated by monitoring the resistance change over time in accelerated tests at temperatures and current densities greater than those seen in normal service. A certain change in resistance, or percentage change in resistance, is taken as the failure criterion. The resistance change is a result of void growth in the Al-alloy line, usually located at a tungsten via. MODEL AND MECHANISMS Figure 1 is a schematic rendering of an interconnect line of length I with a thin redundant refractory layer underlying a thick aluminum layer which has a void of length Al, as wide and thick as the aluminum. The resulting resistance increase is given by
AR
PLhAl Al
R
PAjhL I
T
Al
T'
(1)
where PAMand PL are the resistivities, and hAL and hL are the thicknesses, of the aluminum and underlayer, respectively; y is defined as the ratio of the underlayer sheet resistance to that of the aluminum. As a specific example, consider the case of a TiN underlayer which is one-tenth the aluminum thickness. The resistivity of the TiN is approximately 20 times that of the aluminum, so -y= 200. Therefore, to realize a 100% increase in resistance, Al need only be 0.5% of the line length. Void growth is driven by the magnitude of both thermal and electromigration stresses. As void growth relieves these stresses in the interconnect line, growth slows and the ultimate void size will be self-limited. The maximum void volume is given by V,,oid = whAlt(eT + CEM),
(2)
where ET is the thermal strain, and EEM is the steady-state electromigration-induced strain. The concomitant percentage change in resistance in the interconnect line will therefore saturate with time at a maximum value given by AR -R -
(ET + EEM ) . 423
Mat. Res. Soc. Symp. Proc. Vol. 391 ©1995 Materials Research Society
(3)
Thermal Strain -Al-.
A change in temperature, AT, will introduce a strain in the aluminum interconnect due to differential thermal expansion which can be approximated as ET = (aAl - as, AT,
hL
.
(4)
where &AL and asi are the linear coeffiE cients of thermal expansion (CTE) for the
Data Loading...
