Failure Analysis and Process Improvement for Through Silicon Via Interconnects
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Failure Analysis and Process Improvement for Through Silicon Via Interconnects Bivragh Majeed, Marc Van Cauwenberghe, Deniz S. Tezcan, Philippe Soussan IMEC Kapeldreef 75, B-3001, Leuven, Belgium ABSTRACT Through silicon vias (TSV) is one of the key enabling technologies for 3D wafer level packaging (WLP). This paper investigates the failure causes of TSVs in a “via last” approach and presents process improvement for implementing the TSV. There are many parameter including silicon etch uniformity, dielectric etching at the bottom of the TSV, non-uniform plating and resist residue inside the via that can reduce the yield of the process. We report that one of the main factors contributing to the yield loss is silicon dry etching effects including non-uniformity and notching. A new via shape that is a combination of sloped and straight etching sequence is developed in order to improve silicon dry etch effects. An improved and characterized, notch free uniform silicon etching across the wafer process based on three step etching is presented. An integration flow implementing the optimized parameters with showing electrical interconnection is given in the paper. INTRODUCTION IMEC is investigating two generic approaches for 3D wafer integration that are categorized into via first, 3D SiC, and via last, 3D WLP, strategies [1]. 3D technologies have become one of the main drivers for continuous system miniaturization and driving “More than Moore” applications. [2]. “More than Moore” concept suggests new integration techniques that combine multiple die/wafer with multiple functions into a single module rather than trying to combine vastly different types of circuits on a single die. The main advantage of this approach is to bring together different IC’s and build highly integrated modules with optimized performance, size and cost. TSV are one of the key technologies for realizing “More than Moore” concept for different 3D integration routes. At IMEC, 3D SiC approach aims to create very high density vertical interconnects to allow stacking of die. This approach also referred to as via first, as via are formed during the CMOS processing prior to BEOL. It involves formation of silicon via, dielectric deposition, copper filling, standard BEOL processing followed by bonding the device wafer to a carrier, thinning down to 20 microns and a CMP step to expose the copper plug. These plugs are then used for make interconnection between different dice. IMEC has demonstrated yielding 10K TSV chains with an average via pitch of 10 microns for a via diameter of 5 microns [3]. 3D WLP approaches at IMEC can be divided into two categories depending on the scalability of the process. Both are based on “via last” methodology where the TSV are processed after CMOS and even after wafer thinning process. Hence it is a generic approach and compatible with standard IC wafers allowing direct stacking of wafers or die. We have previously demonstrated yielding via chains of different size ranging from 50-150 microns based on sloped T
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