Formation of End-of-Range Defects in Silcon at Low Temperatures
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FORMATION OF END-OF-RANGE DEFECTS IN SILCON AT LOW TEMPERATURES M.Seibtt,J .Imschweiler and H.-A. Hefnert IV.Physikalisches Institut der Universitit G6ttingen, Bunsenstr. 13-15, 3400 G6ttingen, Federal Republic of Germany, present adress: AT&T Bell Laboratories, rawfords Corner Road, Holmdel, NJ-07733 "TELEFUNKEN electronic GmbH, Theresienstr.2, 7100 Heilbronn, Federal Republic of Germany
ABSTRACT We have used high resolution transmission electron microscopy t%study the formation of end- of- range defects after pre- amorphization due to Ge - implantation and subsequent furnace annealing at temperatures below 550 0 C. It is shown that depending on the annealing conditions two types of extrinsic stacking faults (SFs) are formed, i.e. {113}- defects or Frank- type {(11) SFs. We present a scheme allowing the controlled deposition of Si self- interstitials into {113)- defects, which can be removed more easily than Frank type SFs during subsequent RTA under constraints of low thermal budget. INTRODUCTION Ion implantation has been proven to be a powerful tool for designing shallow junctions in silicon device technology. For applications in ultra large scale integration (ULSI) deep penetration of implants has to be prevented, which is difficult for direct
implantation of low mass ions (e.g.: B) into single- crystalline silicon because of significant channeling tails. One technique frequently applied to solve this problem is pre-amorphization via implantation of isoelectronic atoms like Si or Ge. The main drawback of this technique is the formation of a variety of defects after solid- phaseepitaxial regrowth (SPEG) of the amorphous layer. These are e.g. hairpin dislocations spanning from the original amorphous/crystalline (a/c) interface to the wafer surface [1] or so- called end- of- range (EOR) defects beneath the a/c interface, which are
known to be of extrinsic type, i.e. they are agglomerates of Si self- interstitials (Si) [2]. Various studies mainly using TEM or RBS have been dedicated to the questi ns of how to avoid or remove certain types of defects. As an example, Sands and coworkers [3] have shown that hairpins nucleate at misorientated crystalline islands in the amorphous regions during SPEG. Most studies concerned with extended EOR defects focused on the problem of their redissolution during RTA at high temperatures. Rozgonyi and coworkers reported a scheme for defect- free recrntallization of Ge- implanted Si, which involves a low temperature annealing at 450 C followed by RTA for 10s at 1050 0 C [4-6]. Defectfree SPEG has been reported for silicon after Ge implantation at 27keV followed by a 10s RTA at 950'C [7]. However in recent studies EOR defects have been observed after this combined low- and high- temperature treatment [8,9]. Besides their thermal stability the structure of extended EOR defects observed after ionimplantation and annealing seems also to be a puzzle since extrinsic Frank-type stacking faults ( b =a/3, subsequently referred to {lll}-SFs) or perfect dislocation loops [2] and { 113 -SFs [
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