Formation of silicon nanostructures with a combination of spacer technology and deep reactive ion etching
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NANO EXPRESS
Open Access
Formation of silicon nanostructures with a combination of spacer technology and deep reactive ion etching Daniel CS Bien*, Hing Wah Lee and Siti Aishah Mohamad Badaruddin
Abstract A new method of fabricating high aspect ratio nanostructures in silicon without the use of sub-micron lithographic technique is reported. The proposed method comprises two important steps including the use of CMOS spacer technique to form silicon nitride nanostructure masking followed by deep reactive ion etching (DRIE) of the silicon substrate to form the final silicon nanostructures. Silicon dioxide is used as the sacrificial layer to form the silicon nitride nanostructures. With DRIE a high etch selectivity of 50:1 between silicon and silicon nitride was achieved. The use of the spacer technique is particularly advantageous where self-aligned nanostructures with potentially unlimited lengths are formed without the need of submicron lithographic tools and resist materials. With this method, uniform arrays of 100 nm silicon nanostructures which are at least 4 μm tall with aspect ratio higher than 40 were successfully fabricated. Keywords: Silicon, Nanostructures, Nano-masking, High-aspect ratio, Deep reactive ion etching, Spacers
Background As microdevices shrinks towards nanoscale, formation of high aspect ratio nanostructures will be more challenging. These nanostructures has numerous applications such as photonic crystals [1,2], thermoelectric generators [3], sensors [4], resonators [5], nanocapacitors [6] and nano-molds [7] for nanoimprint lithography. The aspect ratio of the device is defined by the depth to width ratio of the structure. Typically, in semiconductor device fabrication, a combination of sub-micron lithography techniques and etching are commonly used in generating patterns with nano dimensions. Such techniques includes electron beam lithography [8], dip-pen lithography [9], near field scanning probe lithography [10], nanoimprint lithography [7] and x-ray lithography [11]. However, these techniques might not be suitable to produce high aspect ratio nanostructures as there is resist imposed limitations during etching, namely the resist thickness is thin and unable to withstand long durations of high power plasma etching. Alternatively, silicon * Correspondence: [email protected] Nanoelectronics Cluster, MIMOS Berhad, Technology Park Malaysia, Kuala Lumpur 57000, Malaysia
nanostructures or nanowires can also be synthesized by bottoms-up method via chemical vapour deposition [12], laser-ablation [13] and thermal evaporation [14] techniques. However, organising these nanowires into ordered arrays is challenging and the synthesis process often requires the use of metal catalyst or nanopowders which are not compatible with the standard CMOS fabrication processes. In this letter, we demonstrate a new method of forming high aspect ratio silicon nanostructures, where very accurate alignment of the nanostructures can be achieved because the alignment is not determined by the lithographic tool but
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