Improved size dispersion of silicon nanocrystals grown in a batch LPCVD reactor
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Improved size dispersion of silicon nanocrystals grown in a batch LPCVD reactor Y.M. Wana, K.van der Jeugda, T.Baronb, B. De Salvob, P.Murb a ASM Belgium, Kapeldreef 75, B3001 Leuven, Belgium b CEA/LETI, 17 Av,des Martyrs, 38054 Grenoble Cedex 9, France
ABSTRACT Nanocrystal memories are widely invoked as potential solutions to overcome the scaling limitations of conventional FLASH memories beyond the 80nm technology node. In this study, the deposition of uniform silicon nanocrystals has been developed and optimized in a commercially available vertical furnace, an A400 from ASM. It has been shown that low pressure chemical vapor deposition (LPCVD) of nanocrystals is feasible in a batch reactor but with a bad size dispersion of the silicon nanocrystals. To improve the size dispersion of the nanocrystals, a novel 2-step process with silane was introduced. In the conventional 1-step process, the oxide surface is exposed to silane at the same partial pressure and temperature during both nucleation and growth of the silicon nanocrystals. In this novel 2-step process, the surface is first exposed briefly to silane at a higher temperature (580-600oC) and following that, the temperature is lowered to allow selective growth on the existing silicon nuclei over the oxide surface. With such an approach, the nucleation step can be separated from the growth step and consequently the size dispersion can be improved by 50%.
INTRODUCTION To overcome the downscaling limitations of the conventional floating gate FLASH memories beyond the 80nm flash technology node, alternative structures consisting of discrete traps are being investigated [1]. In this work, the growth of silicon nanocrystals was optimized and used as discrete trap for future generations of standalone and embedded Non Volatile Memory. In such cases, the standard polysilicon floating gate is replaced by a discontinuous layer consisting of silicon nanocrystals. However the threshold voltage shift of such nanocrystal memories is limited by the gate surface coverage of the silicon nanocrystals. To obtain a detectable shift of the threshold voltage of the memory, 20% to 40% of the surface should be covered by nanocrystals to ensure that a sufficient amount of charge can be stored. A second critical issue related to these nanocrystal memories is the spread in nanocrystal size and density from one device to another [2]. To overcome these two limitations, a novel 2-step process for silicon nanocrystal deposition was developed. This original technique allows high nanocrystal density (up to 7.4x1011 cm-2) to be obtained by a simple LPCVD approach, and at the same time a strict control over the size dispersion of the nanocrystals.
EXPERIMENTAL For the final integration of these silicon nanocrystals onto memory devices, a thermal oxidation is necessary to form the tunnel oxide. To increase the nanocrystal density up to 1012 cm-2, special chemical treatment has to be preformed to the oxide surface prior to the nanocrystal deposition. A controlled thickness of the thermall
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