Independent Tunneling Reductions Relative to Homogeneous Oxide Dielectrics from I) Nitrided Interfaces and Ii) Physicall
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Mat. Res. Soc. Symp. Proc. Vol. 592 © 2000 Materials Research Society
10' 102 101 1°°
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Tox-eq - 1.6nm
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Fig. 1. (a) Current density-gate voltage (J-V) plots for MOS capacitors with EOT - 2 nm and 3 nm. (b) J-V characteristics of MOS capacitors with plasma deposited nitride/oxide (N/O) stacks compared to device with a homogeneous oxide layer (EOT - 1.9 nm). (c) J-V characteristics for a PMOS FET compared to a device with a homogeneous oxide for EOT - 1.9 nmn. dielectrics, and then from iii) a combination of mono-layer interface nitride and physically thick nitride layers in stacked structures. Reductions in direct tunneling at an -1 V bias are i) a factor of -10 for interface nitridation for substrate accumulation at EOTs of -2 and 3 nm, ii) a factor of -10 for EOT -1.9 nm, for different ratios of nitride to oxide thickness, - 4:1 and 0.67:1, and iii) a factor of > 200 for EOT -1.6 nm, for the combination of interface nitridation, and increased physical thickness by a nitride for oxide substitution. Comparisons are made between devices with the same Vti in (a) or scaled for differences in Vtm as in (b) The approximately equal tunneling reductions in ii) for different N/O ratios is consistent with the tunneling mass of electrons in the nitride films being reduced by a factor of one half with respect to that of electrons in Si0 2 ; i.e., from - 0.5 mo to - 0.25 mo, where mo is the free electron mass [15]. 101 101 100
100
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1
2
3
4
8
10
12
14
16
18
20
22
24
26
Tox-eq (Angstrom) for NIO Films
Vg (V)
Fig. 2. (a) Jg versus Vg for PMOS FETs with EOT from 1.3 to 2.4 nm. (b) Scaling of Jg versus EOT for PMOS FETs of (a). Limiting EOT for Jg < 1 A/cm-2 is less than 1.1 nm.
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Applied Voltage (V)
Fig. 3. Jg versus Vg for NMOS FETs with plasma-grown non-nitrided Si-Si0 2 interfaces and RPECVD oxide, nitride and oxyntirde gate dielectric layers. Also shown are C-V characteristics. Figures 2(a) and (b) include respectively (a) J-V characteristics for PMOS devices with stacked oxide/nitride dielectrics for EOT from about 2.4 to 1.3 rni, and (b) a plot of Jg versus EOT for a bias voltage of
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