Large-Grain Polysilicon Films with Low Intragranular Defect Density by Low-Temperature Solid-Phase Crystallization
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Large-Grain Polysilicon Films with Low Intragranular Defect Density by LowTemperature Solid-Phase Crystallization Xiang-Zheng Bo, Nan Yao†, and J. C. Sturm Center for Photonics and Opti-Electronic Materials, Department of Electrical Engineering, Princeton University, Princeton, New Jersey 08544, U.S.A. † Princeton Materials Institute, Princeton University, Princeton, New Jersey 08544, U.S.A. ABSTRACT Solid phase crystallization (SPC) of a-Si: H at 600 °C was investigated by transmission electron microscopy (TEM) and Raman spectroscopy in a cantilever structure, where the underlying SiO2 was removed prior to the crystallization. The absence of the underlying oxide leads to both a higher grain size and a lower intragranular defect density. The grain size increases from 0.6 µm in regions with the underlying oxide to 3.0 µm without the underlying oxide, and the intragranular defect density decreases one order of magnitude from ~ 1011 cm-2 to ~ 1010 cm2 . The improvements in material quality without the lower a-Si/SiO2 interface are thought to be due to a lower nucleation rate and a lower tensile stress with an easier silicon atomic rearrangement at the lower silicon interface. INTRODUCTION Polysilicon thin film transistors (TFTs) are used in active-matrix-liquid-crystal displays (AMLCD) [1] and as upper-layer devices for three-dimensional VLSI [2]. For such active layers of TFTs, polycrystalline silicon crystallized from amorphous silicon by solid-phase crystallization (SPC) has attracted much interest. The electrical characteristics of polysilicon TFTs are strongly dependent on the polysilicon microstructure. The electron carrier mobility in polysilicon TFTs is typically < 100 cm2/Vs, which is much less than that in single-crystalline silicon MOSFETs. Grain boundaries and intragranular defects (microtwins and dislocations) are electrical potential barriers and scattering sites, which decrease the mobility. Polysilicon films with a larger grain size and lower intragranular defect density have been a continual goal [3-6]. To date, there are two methods to decrease the density of intragranular defects of polysilicon films crystallized from a-Si: high-temperature (>750 °C) annealing [7] and laser crystallization [8]. However, high-temperature processing cannot be used in AMLCD TFTs, which are fabricated on glass substrates with a strain point less than 650 °C. Compared with the furnace annealing, laser crystallization has the potential disadvantages of high-cost and poor film uniformity. This paper examines how removing the underlying oxide before crystallization step can increase grain size and reduce defect density within grains, while maintaining the process temperature ≤ 600 °C. EXPERIMENT AND RESULTS Figure 1 shows the fabrication process of the cantilever structure of suspended a-Si. After depositions of 100nm-thick Si3N4 and 2µm-thick SiO2 on a silicon substrate, a-Si was
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