Negative Bias Temperature Instability for P-channel of LTPS Thin Film Transistors with Fluorine Implantation
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1066-A16-03
Negative Bias Temperature Instability for P-channel of LTPS Thin Film Transistors with Fluorine Implantation Chyuan-Haur Kao, and W. H. Sung Electronics Engineering, Chang Gung University, 259 Wen-Hwa 1st Road, Kwei-Shan, Tao-Yuan, 333, Taiwan ABSTRACT This paper studies the impact of LTPS (low temperature polycrystalline silicon) TFTs with fluorine implantation under NBTI (Negative bias temperature instability) stress. The fluorinated TFTs’ devices can obtain better characteristics with samller threshold voltage shift, lower trap states and lower subthreshold swing variation. Therefore, the fluorine implantation does not only improve initial electrical characteristics, but also suppresses the NBTI-induced degradation. INTRODUCTION Low-Temperature Polycrystalline Silicon thin-film transistors (LTPS TFTs) have attracted much attention due to high possibility for the integration of peripheral circuits and active matrix [1-2]. Compared with amorphous TFTs, the LTPS TFTs have better performance, higher field-effect mobility, and better reliability stability [3]. Negative bias temperature instability (NBTI) has become one increasingly important issue especially for thin gate oxide in p-channel MOSFETs [4-5]. In general, the degradation mechanism about the NBTI stress in MOSFETs is mainly attributed to the generation of fixed oxide charges and interface trap states [6]. In polycrystalline silicon TFTs, some studies have also found the performance degradation after NBTI stress, which may generate interface states and grain boundary trap states in the polysilicon/polyoxide interface and polysilicon grain boundaries [7-9]. This paper studies the fluorine implantation into the LTPS P-channel TFTs after the NBTI stress can obtain better characteristics with small threshold voltage shift, lower interface states and lower subthreshold swing variation. Since the implanted fluorine into the TFT channel poly-Si can terminate the poly-Si defects or trap states to form more strong bonds for reliability improvements. Therefore, the fluorine implantation did not only improve the initial electrical characteristics, but also suppress the NBTI-induced degradation.
EXPERIMENTAL DETAILS The P-channel LTPS TFTs were fabricated on thermally oxidized silicon wafers. An amorphous-silicon film of about 130-nm was initially deposited at 5500C by low-pressure chemical vapor deposition (LPCVD) using pure SiH4 gas. It was then furnace-annealed at 6000C for 24 hours in N2 ambient gas to recrystallize the silicon films. Fluorine ions with a dosage of 2×1015 cm-2 was implanted at 11 keV, and then activated at 6000C in an N2 ambient. After defining the active region, a 50 nm thickness of gate-oxide was deposited by a PECVD system with gas mixtures of SiH4 and N2O at 3000C. Another 200-nm polysilicon film was deposited at 6200C and then patterned as the gate electrode. A self-aligned boron implantation at a dose of 5x1015 cm-2 was used to dope the drain, source, and gate areas. The dopants were then activated at 6000C for 8 hr in an N2 amb
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