Threshold Voltage Optimization with Ion Shower Implantation for Polysilicon Thin-film Transistors
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A17.7.1
Threshold Voltage Optimization with Ion Shower Implantation for Polysilicon Thin-film Transistors B. D. Choi, D. C. Choi, C. Y. Im, K. H. Choi, C. H. Yu, R. Kakkad and H. K. Chung Advanced Technology Institute, Samsung SDI, Giheung, Yongin, Kyoungki, 442-391, S. Korea ABSTRACT In this paper, we present the results of ion shower implantation to adjust threshold voltages on ELC (excimer laser crystallized) poly silicon thin film transistors. We observed that the threshold voltages of poly Si TFT strongly depended on the shower implantation dose, not the shower implantation energy for the 500 Å-thick active silicon layer. The threshold voltages for the reference, dose 5×1011 cm-2, and 1×1012 cm-2 cases were 0.30V, 1.25V, and 2.04V, respectively. We conclude that the threshold voltage can be appropriately adjusted by tuning the dose of the counter doping shower implant and its DIBL can still be suppressed to within an acceptable level. INTRODUCTION Low temperature poly silicon (LTPS) TFTs have been extensively studied for fabrication of the pixels, drivers, digital-to-analog converters (DACs), and timing controllers for the display technology [1,2]. For system-on-panel (SOP) applications, the device dimensions need to be continuously reduced to accommodate a greater degree of integration of circuit and memory components on the LTPS panels. As the LTPS poly silicon TFT technology evolves into near the sub-micrometer regime, control of the device threshold voltage is becoming a major issue. As the SOP technology requires the lowest power dissipation and the highest packing density, the TFT device parameters such as threshold voltage, drain-induced barrier lowering (DIBL) coefficient, and n-TFT/p-TFT on-current ratio for digital circuitry must be controlled precisely. In order to achieve the precise control of n and p TFT threshold voltages to get the desired n-TFT/pTFT on-current ratio, it is necessary to do an implant doping of the channel region. Standard ion implantation technique is not suitable for large area glass substrates. Ion shower implantation is one solution because it uses a large area ion beam extracted from a plasma source [3-5]. Here we present an experimental study of the ion shower implantation in the n-TFT channel regime and evaluate its electrical characteristics in order to minimize DIBL effect with various implant doses. By employing a threshold adjust implant, we improved device-to-device uniformity and the n-TFT/p-TFT on-current ratio for inverter circuits. DEVICE FABRICATION We used glass substrates with SiO2 buffer layer to fabricate the low temperature polysilicon (LTPS) TFTs. First, 500 Å-thick amorphous silicon films were deposited on the glass substrates by plasma enhanced chemical vapour deposition (PECVD). Then, excimer laser annealing (ELA) was utilized to crystallize a-Si film for low temperature process followed by polysilicon active area patterning. After the active area patterning, the n-TFT channels were implanted w-
A17.7.2
Gate metal SiO2 Channel doping
Polysilicon Buf
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