Performance Improvement of Vector-Radix Decimation-in-Frequency 3D-DCT/IDCT Using Variable Word Length
- PDF / 1,285,079 Bytes
- 14 Pages / 439.37 x 666.142 pts Page_size
- 14 Downloads / 161 Views
Performance Improvement of Vector-Radix Decimation-in-Frequency 3D-DCT/IDCT Using Variable Word Length V. Arunachalam1 · Alex Noel Joseph Raj2
· S. Deepika1
Received: 8 February 2020 / Revised: 16 September 2020 / Accepted: 21 September 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract High-speed video coding and compression are extensively used in many IoT applications with optimum data usage and resolution using three-dimensional discrete cosine transforms (3D-DCT). We propose an efficient hardware implementation for highspeed vector-radix decimation-in-frequency (VR-DIF) 3D-DCT with an optimum area and power consumption. In the previous implementation, the data path arithmetic units used a fixed word length (either 16 or 18 or 21 bits), whereas the proposed architecture uses the range of word length from 11 bits (1-bit sign, 1-bit integer and 9-bit fraction) to 20 bits (1-bit sign, 10-bit integer and 9-bit fraction) to achieve lower silicon area and power consumption. The architecture is optimally pipelined to achieve high processing speed (above 3 Giga samples/s). To test the proposed architecture, an 8 × 8 × 8 video cube with a pixel depth of 8 bits is considered. The arithmetic functional units such as signed adder/subtractor and cosine coefficient multipliers required for implementing 8×8×8 3D-DCT/IDCT processor is designed with the proposed variable word length. The core of VR-DIF 3D-DCT/IDCT with the variable word length is implemented using TSMC 90 nm technology library. The proposed architecture consumes 26.5% and 23.2% lesser area and power, respectively, than the existing fixed word length 3D-DCT-II implementation tested with a maximum frequency of 653 MHz. Keywords 3D-DCT/IDCT · Cosine coefficient · Variable word length · VR-DIF
B
Alex Noel Joseph Raj [email protected] V. Arunachalam [email protected] S. Deepika [email protected]
1
Department of Micro and Nano Electronics, School of Electronics Engineering, Vellore Institute of Technology, Vellore, India
2
Key Laboratory of Digital Signal and Image Processing of Guangdong Province, Department of Electronic Engineering, College of Engineering, Shantou University, Shantou, China
Circuits, Systems, and Signal Processing
1 Introduction Data compression is the crucial step in encoding of any signal in digital form as it reduces the transmission bandwidth and storage space. Also, it is the first step towards any domain transformation, which decides the efficiency of the encoding process and plays a significant role in attaining the de-correlation from the highly correlated realworld signals such as video sequences. The discrete cosine transform (DCT) is helpful to compress the image/frame in each butterfly stage with different encoding coefficients and results achieves optimum compression efficiency [1,2]. The three-dimensional discrete cosine transform (3D-DCT) has been a standard transform technique for video coding. The selection of a sub-video size of 8 × 8 × 8 is the best choice based on
Data Loading...
