Post-Bond Test Wrappers and Emerging Test Standards
Throughout this book, methods and architectures have been discussed for performing pre-bond and post-bond test in 3D SICs. Many of these methods, such as those discussed in Chaps. 4 and 5, were designed to be compatible with emerging test standards. This
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sign-for-Test and Test Optimization Techniques for TSVbased 3D Stacked ICs Foreword by Vishwani Agrawal
Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
Brandon Noia • Krishnendu Chakrabarty
Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs Foreword by Vishwani Agrawal
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Brandon Noia ECE, Duke University Durham, NC, USA
Krishnendu Chakrabarty ECE, Duke University Durham, NC, USA
ISBN 978-3-319-02377-9 ISBN 978-3-319-02378-6 (eBook) DOI 10.1007/978-3-319-02378-6 Springer Cham Heidelberg New York Dordrecht London Library of Congress Control Number: 2013955016 © Springer International Publishing Switzerland 2014 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Exempted from this legal reservation are brief excerpts in connection with reviews or scholarly analysis or material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Duplication of this publication or parts thereof is permitted only under the provisions of the Copyright Law of the Publisher’s location, in its current version, and permission for use must always be obtained from Springer. Permissions for use may be obtained through RightsLink at the Copyright Clearance Center. Violations are liable to prosecution under the respective Copyright Law. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. While the advice and information in this book are believed to be true and accurate at the date of publication, neither the authors nor the editors nor the publisher can accept any legal responsibility for any errors or omissions that may be made. The publisher makes no warranty, express or implied, with respect to the material contained herein. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)
To my parents for their boundless support. —Brandon Noia
To all my truly outstanding students over the years. —Krishnendu Chakrabarty
Foreword
Present trends in the electronics industry indicate that the three-dimensional stacked integrated circuit (3D SIC) is a technology with potential for wide scale application. So, is this 3D SIC just an extension of a flat (2D) integrated circuit? If this device is three dimensional then are we going to build 4D IC in the future as our world is believed to have a fourth dimension of time? Let me settle t
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