Processing Impact on Electrical Properties of Lanthanum Silicate Thin Films
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0917-E10-03
Processing Impact on Electrical Properties of Lanthanum Silicate Thin Films Jesse S. Jur1, Daniel J. Lichtenwalner2, Naoya Inoue3, and Angus I. Kingon2 1 Department of Materials Science and Engineering, North Carolina State University, 1001 Capability Drive, 221 Research Bldg. 1, Campus Box 7919, Raleigh, North Carolina, 27695 2 Department of Materials Science and Engineering, North Carolina State University, Raleigh, North Carolina, 27695 3 System Devices Research Labs, NEC, Sagamihara, Kanagawa, 229-1198, Japan ABSTRACT The consequence of tungsten metal purity on the electrical properties of an annealed MOS gate stack with a lanthanum silicate gate dielectric has been investigated. Optimization of the electrical and physical properties of a device with any given dielectric requires the proper choice of metal gate electrode and capping layer. This study is intended to show the importance of tungsten capping layer processing optimization and subsequent effects on the equivalent oxide thickness, fixed charge, and density of interface states of La-Si-O gate dielectric MIS devices. In the experiment, La-Si-O films of physical thickness of 1.6 nm were deposited on a Si substrate, subsequently depositing TaN as the gate electrode and W as a capping layer. A post metallization anneal in flowing nitrogen at 1000°C for short times resulted in widely different measured properties of the MIS devices, dependent on the quality of the tungsten deposited. XRD and SIMS profiles of the gate stacks showed a clear relationship between concentration of oxygen and processing of the tungsten. A 1000°C, 10 sec anneal resulted in EOT values of 1.1 nm and 2.2 nm on gate stacks with low and high oxygen concentration in the tungsten, respectively. Defect densities decreased with increased anneal temperature and time, and annealing with low oxygen-concentration tungsten resulted in higher effective fixed charge. SIMS data suggests that oxygen in the tungsten diffuses to the Si/La-Si-O interface through the TaN electrode, resulting in the observed differences in the defect densities and EOT. INTRODUCTION As MOSFET devices are scaled, a high-κ gate dielectric is needed to replace SiO2 films due to their high leakage currents when thickness decreases below 1.0 nm [1]. The implementation of a high-κ dielectric to replace SiO2 in a MOSFET device requires an operational optimization of the gate stack (Metal/Oxide/Semiconductor) while adhering to the stringent requirements to process the transistor device. The severe thermal requirement needed for source/drain dopant activation typically results in an increase in the oxide thickness and unwanted reaction between different layers of the gate stack. High defect levels found in high-κ materials and at the Si interface result in a decrease in the mobility of the semiconductor and unwanted threshold voltage values. The intrinsic electrical properties required for alternate high-κ materials include a high dielectric constant, high band gap energy, and large band offsets when in contact with S
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