Profiling Different Kinds of Generated Defects at Elevated Temperature in Both SiO 2 and High-k Dielectrics
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1252-I05-08
Profiling different kinds of generated defects at elevated temperature in both SiO2 and high-k dielectrics S. Sahhafa,b, R. Degraevea, M.B. Zahida, and G. Groesenekena,b a b
IMEC, Kapeldreef 75, B-3001, Heverlee, Belgium KULeuven , ESAT Department, Leuven , Belgium
Corresponding author: Sahar Sahhaf, IMEC, Kapeldreef 75, B-3001 Heverlee, Belgium. Tel.: +32 (0) 16 28 76 69. E-mail: [email protected]
ABSTRACT In this work, the effect of elevated temperature on the generated defects with constant voltage stress (CVS) in SiO2 and SiO2/HfSiO stacks is investigated. Applying Trap Spectroscopy by Charge Injection and Sensing (TSCIS) to 6.5 nm SiO2 layers, different kinds of generated traps are profiled at low and high temperature. Also the Stress-Induced Leakage Current (SILC) spectrum of high-k dielectric stack is different at elevated temperature indicating that degradation and breakdown at high temperature is not equivalent to that at low temperature and therefore, extrapolation of data from high to low T or vice versa is challenging. INTRODUCTION Due to internal heating, the operating temperature of advanced CMOS technology is considerably higher than ambient room temperature. Consequently, several stress-induced degradation phenomena that limit the circuit reliability are accelerated as compared to room temperature evaluations on test structures. Understanding the temperature dependence of oxide degradation under uniform stress conditions is generally accepted as a critical issue that should be accounted for in reliability projections. Especially in gate stacks that contain high-k materials, the number of published studies on the temperature dependence of degradation is still limited. In this work, we characterize traps generated at elevated temperature in both SiO2 and a selected SiO2/HfSiO gate dielectric stack. The obtained results will make us alert about the limitations in extrapolating the data (e.g. breakdown time) from test temperature to another temperature. We demonstrate that the generation of oxide defects changes as a function of temperature. Degradation and breakdown at high temperature is therefore not equivalent to that at low temperature. Similar observations have already been reported by Kaczer et al. on single layer SiO2 gate dielectric [1], using indirect argumentation and which is confirmed by the trap characterization results presented here. As a consequence, straightforward extrapolation of Stress-Induced Leakage Current (SILC) and Time-Dependent Dielectric Breakdown (TDDB) data from high to low T or vice versa is problematic.
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EXPERIMENTAL The first group of samples characterized in this work consists of electrically-stressed NMOS transistors fabricated at IMEC using a CMOS process with conventional 6.5 nm gate oxide films. The second group of samples is fabricated using a standard high-k/MG integration flow [2]. 3nm HfSiO (50% Hf) was deposited by Atomic layer deposition (ALD) on a chemical SiO2 interface layer resulting from IMEC clean [3]. DPN / PNA were done to incorp
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