Radix-8 Modified Booth Fixed-Width Signed Multipliers with Error Compensation
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RESEARCH ARTICLE-ELECTRICAL ENGINEERING
Radix-8 Modified Booth Fixed-Width Signed Multipliers with Error Compensation Govinda Rao Locharla1
· Kamala Kanta Mahapatra2 · Samit Ari2
Received: 30 March 2020 / Accepted: 29 August 2020 © King Fahd University of Petroleum & Minerals 2020
Abstract The Booth multipliers require lower number of addition operations compared to the traditional multipliers. Further, higher radix Booth multiplier requires lesser number of adders in its circuit implementation. Multiply and accumulate (MAC) unit plays a crucial role in digital signal processing circuits. Handling the data in area-efficient MAC circuits is challenging since the data word length closely doubles on each multiplication. The data path of higher word length possesses higher hardware complexity. However, such hardware complexity can be minimized by deploying the fixed-width multipliers (FWM) in MAC circuits. In FWMs, the multiplication result of X L−bits × Y L−bits is rounded to the higher significant L bits by truncating the rest of lower significant bits. Nevertheless, this truncation introduces the error in multiplication result. This paper presents a radix-8 Booth-based fixed-width signed multipliers with error compensation. Moreover, the estimation of bias value for the error compensation in radix-8 Booth FWM is presented. Accuracy of the fixed-width multiplication with the proposed compensation is analyzed. In addition, the multiplier circuits based on the proposed methods are designed and implemented and the experimental results are discussed. Keywords Application-Specific Integrated Circuit (ASIC) · Fixed-Width Multiplication (FWM) · Error compensation · Booth Multiplier
1 Introduction The complex multiplier plays a crucial role in the DSP architectures like MDC/MDF FFT/IFFT processor. In such applications, the complex multipliers are used for interstage and intra-stage twiddle coefficient multiplications. A traditional L-bit signed multiplication results 2L-bit product. Therefore, the word length of the data path is significantly increases from one stage to another across the pipeline architecture. In order to overcome such issues, the result of each L-bit multiplication can be confined to L bits by truncat-
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Govinda Rao Locharla [email protected] Kamala Kanta Mahapatra [email protected] Samit Ari [email protected]
1
Department of Electronics and Communication Engineering, GMR Institute of Technology, Rajam, Andhra Pradesh, India
2
Department of Electronics and Communication Engineering, National Institute of Technology, Rourkela, Odisha, India
ing the lower significant L bits [1–4] and such operation is called the fixed-width multiplication. This multiplication practice saves power and area significantly, but introduces the truncation error. The Booth multiplication method is popular since it offers low hardware complexity, better speed and power performance [1–5]. Moreover, the higher radix (R) Booth algorithm employs lower number of partial product rows that is approximately equal to L/k
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