Rapid Prototyping of Digital Systems A Tutorial Approach
Rapid Prototyping of Digital Systems, Second Edition provides an exciting and challenging laboratory component for an undergraduate digital logic design class. The more advanced topics and exercises are also appropriate for consideration at schools that h
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RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition A Tutorial Approach
James O. Hamblen Georgia Institute of Technology
Michael D. Furman Georgia Institute of Technology
KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW
eBook ISBN: Print ISBN:
0-306-47635-5 0-7923-7439-8
©2002 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print ©2001 Kluwer Academic Publishers Dordrecht All rights reserved No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: and Kluwer's eBookstore at:
http://kluweronline.com http://ebooks.kluweronline.com
Table of Contents 1
Tutorial I: The 15 Minute Design 1.1
Design Entry using the Graphic Editor
6
1.2
Compiling the Design
9
1.3
Simulation of the Design
10
1.4
Downloading Your Design to the UP 1 or UP 1X Board
12
1.5
The 10 Minute VHDL Entry Tutorial
14
1.6
Compiling the VHDL Design
17
1.7
The 10 Minute Verilog Entry Tutorial
17
1.8
Compiling the Verilog Design
21
1.9
Timing Analysis
22
1.10
The Floorplan Editor
23
1.11 Symbols and Hierarchy
24
1.12 Functional Simulation
24
1.13
25
For additional information
1.14 Laboratory Exercises
2
3
2
25
The Altera UP 1 and UP 1X CPLD Boards
30
2.1
Programming Jumpers
31
2.2
MAX 7000 Device and UP 1 I/O Features
31
2.3
MAX and FLEX Seven-segment LED Displays
31
2.4
FLEX 10K Device and UP 1 I/O Features
34
2.5
Obtaining a UP 1 or UP 1X Board and Power Supply
36
Programmable Logic Technology
38
3.1
CPLDs and FPGAs
41
3.2
Altera MAX 7000S Architecture – A Product Term CPLD Device
42
3.3
Altera FLEX 10K Architecture – A Look-Up Table CPLD Device
43
3.4
Xilinx 4000 Architecture – A Look-Up Table FPGA Device
47
vi
Rapid Prototyping of Digital Systems 3.5
Computer Aided Design Tools for Programmable Logic
49
3.6
Next Generation FPLD CAD tools
50
3.7
Applications of FPLDs
50
3.8
Features of New Generation FPLDs
50
3.9
For additional information
51
3.10
Laboratory Exercises
52
4
Tutorial II: Sequential Design and Hierarchy
54
4.1
Install the Tutorial Files and UP1core Library
54
4.2
Open the tutor2 Schematic
54
4.3
Browse the Hierarchy
56
4.4
Using Buses in a Schematic
57
4.5
Testing the Pushbutton Counter and Displays
58
4.6
Testing the Initial Design on the UP 1 Board.
59
4.7
Fixing the Switch Contact Bounce Problem
60
4.8
Testing the Modified Design on the UP 1 Board.
61
4.9
Laboratory Exercises
61
5 UP1core Library Functions
66
5.1
UP1core DEC_7SEG: Hex to Seven-segment Decoder
67
5.2
UP1core Debounce: Pushbutton Debounce
68
5.3
UP1core OnePulse: Pushbutton Single Pulse
69
5.4
UP1core Clk_Div: Clock Divider
70
5.5
UP1core VGA_Sync: VGA Video Sync Generation
71
5.6
UP1core CHAR_ROM: Character Generation ROM
73
5.7
UP1core Keyboard: Read Keyboard Scan Code
74
5.8
UP1core Mouse:
