Reduced Pressure - Chemical Vapor Deposition of high Ge content (20% - 55%) SiGe virtual substrates
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Reduced Pressure - Chemical Vapor Deposition of high Ge content (20% - 55%) SiGe virtual substrates Y. Bogumilowicz (1), J.M. Hartmann, F. Laugier, G. Rolland and T. Billon, CEA-DRT, LETI / D2NT & DPTS, CEA / GRE - 17, Avenue des Martyrs 38 054 Grenoble Cedex 9, France. V. Renard (2), E.B. Olshanetsky (3), O. Estibals (2), Z.D. Kvon (3) and J.C. Portal (2,4) GHMFL, MPI -FKF / CNRS, BP-166, 25, Avenue des Martyrs, 38 042 Grenoble Cedex 9, France (1) STMicroelectronics, 38 921 Crolles Cedex, France. (2) INSA Toulouse, 31077 Toulouse Cedex 4, France. (3) Institute of Semiconductor Physics, Novosibirsk 630 090, Russia. (4) Institut Universitaire de France, 75005 Paris, France. Abstract : We have studied the strain state, film and surface morphology of SiGe virtual substrates (Ge concentrations in-between 20% and 55%) grown by reduced pressure – chemical vapor deposition. The macroscopic degree of strain relaxation of those virtual substrates is equal to 97.2 ± 1.5%. The misfit dislocations generated to relax the lattice mismatch between Si and SiGe are mostly confined inside the graded layer. Indeed, the threading dislocations density obtained for Ge concentrations of 20% and 26% is indeed typically of the order of 7.5 ± 2.5 105 cm-2. Low surface root mean square roughness have been obtained, with values in-between 2 and 5 nm. In order to check the electronic quality of our layers, we have grown a MODFET-like heterostructure, with a buried tensile-strained Si channel 8 nm thick embedded inside SiGe 26%. We have obtained a well-behaved 2-dimensional electron gas in the Si channel, with electron sheet densities and mobilities at 1.45K of 5.4x1011 cm-2 and 212 000 cm2 V-1 s-1, respectively.
1- Introduction : Bandgap engineering by controlling either the strain or the Ge content significantly improves the performances of Si-based devices such as MOdulation Doped Field Effect Transistors (MODFETs) [1-2] or Metal Oxide Semiconductor FETs (MOSFETs) [3-4]. The lattice mismatch inherent to the Si / SiGe system (4.2 % for pure Ge) leads to the presence of threading dislocations and surface undulations (“cross-hatching”) for thick SiGe films grown on Si (001). Both are detrimental to the device performances of Si / SiGe heterostructures, since they lead in a 2D electron or hole gas to a lowering of the drift mobility and cause difficulties in device processing. Growing a linearly or step graded Si1-wGew graded layer followed by a thick constant composition Si1-xGex (0 ≤ w ≤ x) buffer layer (the resulting structure is called a “virtual substrate”) ensures that the lattice mismatch is relaxed gradually, leading to a bending of the misfit dislocations inside the graded layer and thus to a reduction of the threading dislocation density in the nearly fully relaxed constant composition layer on top. However, strain relaxation generates major surface undulations along the directions [5].
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In this paper, we report on the strain state, the spatial distribution of misfit dislocations and the surface morphology of high Ge c
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