Reliability of Nitrided Oxides in N- and P-type 4H-SiC MOS Structures
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J8.4.1
Reliability of Nitrided Oxides in N- and P-type 4H-SiC MOS Structures Sumi Krishnaswami, Mrinal K. Das, Anant K. Agarwal, John W. Palmour Cree Inc., 4600 Silicon Drive, Durham, NC 27703 Tel: (919) 313-5980; Fax: (919) 313-5696; Email: [email protected] Abstract TDDB measurements of NMOS capacitor fabricated with 1200°C dry oxide with 1300°C N2O anneal were performed at 175°C and 300°C under high positive bias stress. The devices are biased into strong accumulation mode such that the field in the oxide is high enough to collect breakdown data in a reasonable period of time. We observe that at 175°C, a 100-year Mean Time to Failure (MTTF) is obtained at an electric field of 3 MV/cm in the oxide. The TDDB measurement has also been performed at 300°C where lifetime has been reduced by a few orders of magnitude, but with an acceptable 100-year MTTF. Recent reliability results on similarly oxidized MOSFETs have shown failures along the same trend as the n-type capacitors, indicating that MOSFETs and MOS capacitors can have similar reliability despite inherent processing and structural differences. PMOS capacitors fabricated with the aforementioned dry + N2O process as well as capacitors fabricated using the low DIT nitridation techniques show acceptable MTTF of 100 years at the nominal operating electric field of 3 MV/cm. Introduction One of the attractive features of MOS-based silicon carbide devices is their potential use for high temperature and high power applications. Earlier problems with high interface trap density (DIT) and low mobility on Si (0001) face of 4H-SiC MOS structures have been steadily improved via nitridation annealing with DIT reported as low as 1x1011 cm-2.eV-1 near EC and mobility approaching 100 cm2/V-s [1][2]. However, the use of such devices will ultimately be limited by the gate oxide integrity and reliability. The concerns about the gate oxide reliability stem from the fact that the barrier height from the SiC conduction band to the oxide conduction band is only 2.7 eV as compared to 3.1 eV in a silicon MOS system. Figure 1 shows how the bands line up for the silicon and 4H-SiC MOS systems [3]. Under low gate voltages, corresponding typically to oxide electric fields, ξox ≤ 3 MV/cm, the gate current flowing in the oxide is negligible. As the gate voltage increases, the electric field in the oxide also increases, resulting in large current flow due to Fowler-Nordheim tunneling of the carriers into the oxide from the conduction or valence band of the SiC [3,4] as shown in figure 2. Large gate currents in the oxide can result in premature breakdown leading to failure of the device. Thus, the reduced barrier existing at the oxide-semiconductor interface under high voltages offset the high power benefit that one gains from the 3x wider bandgap of the 4H-SiC. Hence, the gate oxide integrity and reliability is a challenging hurdle to overcome. In MOSFET devices, during the blocking mode of operation (off state), the device typically supports the very high field, of the order of ~1 MV
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