Silicon Through-hole Interconnection for 3D-SiP Using Room Temperature Bonding
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0970-Y05-01
Silicon Through-Hole Interconnection for 3D-SiP Using Room Temperature Bonding Naotaka Tanaka1, Yasuhiro Yoshimura1, Takahiro Naito2, and Takashi Akazawa2 1 Mechanical Engineering Research Laboratory, Hitachi, Ltd., 832-2, Horiguchi, Hitachinaka, 312-0034, Japan 2 Renesas Technology Corp., 20-1, Josuihon-cho, Kodaira, 187-8588, Japan
ABSTRACT The wire bonding technique has been used for conventional 3D-stacked packages. However, it requires an additional bonding area on the substrate and long wires for connecting a chip to a substrate. In this study, a method is described for interconnecting stacked chips using through-hole electrodes. Electrical interconnection between the chips is achieved by simply applying a compressive force at room temperature to a conventional chip with multiple gold stud bumps. The basic concept of the proposed method was validated using TEG chip with throughhole electrodes. Use of this technology eliminates the need for wire connecting areas, enabling packages to be made smaller and thinner. For example, the package thickness is available to achieve 0.5 mm in two chip layers and 1.0 mm or less in ten chip layers with this technology, against the two chips layers using wire bonding becomes approximately 1.25mm thickness. Use of this method should facilitate the production of ultra-slim, high-performance system-inpackage (SiP) products. INTRODUCTION In rapidly growing market sectors, such as mobile information devices, SiP technology, in which multiple LSI chips are stacked three-dimensionally, is attracting attention as a means of greatly reducing the mounting area of electronic components to improve system performance while reducing system size1–5. Wire bonding has been used for conventional 3D-stacked packages to connect stacked chips. Since this technique provides a high degree of freedom for connecting chips to substrates, it is well suited for connecting multiple LSI chips to substrates. However, it requires an additional bonding area on the substrate and long wires for connecting chips to substrates. Therefore, among the several options for 3D stacking, chip-stacking using through-hole electrodes is an attractive technology for fabricating ultra-slim, high-performance SiPs because of the extremely short wiring length between chip electrodes. In response to this, the Association of Super-Advanced Electronics Technology (ASET) developed a 3D die-stacked module, in which four ultra-thin chips (50-µm thick) are vertically stacked and electrically interconnected between Cu-filled through-hole vias2. We developed a new way to interconnect stacked chips using through-hole electrodes with a lower cost and shorter turn around time (TAT)5. Stacked chips are electrically interconnected simply by applying a compressive force at room temperature to a conventional chip with multiple gold stud bumps.
SILICON THOUGH-HOLE INTERCONNECTION Room temperature bonding method Our method is illustrated in Fig. 1. Multiple through-hole electrodes are formed on the backside of the lower chips. Go
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