Simulation of a single dopant nanowire transistor
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Simulation of a single dopant nanowire transistor Asen Asenov1,2 and Vihar Georgiev1 1 Device Modeling Group, School of Engineering, University of Glasgow, G12 8LT, Glasgow, UK 2 Gold Standard Simulations, Ltd., G12 8LT, Glasgow, UK ABSTRACT Nowadays the silicon technology is capable of delivering sub-10 nm devices where ‘every atom counts’. Manipulation of atoms with high precision on such a scale, in principle, can lead to technological innovations, such as transistors with extremely short gate length, quantum computing components and optoelectronic devices. One possible strategy to create this next generation of devices is to precisely place individual discrete dopants (such as phosphorous atoms) in a nanoscale transistor. In this paper, we report a systematic study of quantum transport simulation of an impact that precisely positioned dopants have on the performance of ultimately scaled gate-all-around silicon nanowire transistors (SNWT) designed for digital circuit applications. Due to strong inhomogeneity of self-consistent electrostatic potential, a full 3-D real-space Non Equilibrium Green’s Function (NEGF) formalism is used. The simulations are carried out for an n-channel NWT with a 2.2 x 2.2 nm2 cross-section and a 6 nm channel length, where locations of precisely arranged dopants in the source drain extensions and in the channel region have been varied. The individual dopants act as localized scatters and, hence, impact of electron transport is directly correlated to the position of the single dopants. As a result, a large variation in the ON-current and modest variation of the subthreshold slope are observed in the ID-VG characteristics when comparing devices with microscopically different discrete dopant configuration. Introducing of channel surface roughness in the Ch Sym 1 wire induces a threshold voltage shift and ONcurrent variation in the device due to scattering. The variations of the current-voltage characteristics are analyzed with reference to the behaviour of the transmission coefficients. Our calculations provide guidance for a future development of the next generation components with sub-10 nm dimensions for the semiconductor industry. INTRODUCTION Nanotechnology provides powerful tools and techniques to control individual atoms or molecules in atomic scale structures and devices. Manipulation of atoms with high precision on such a scale, in principle, can lead to technological innovations, such as transistors with extremely short gate length [1], quantum computing components [2] and optoelectronic devices [3]. One possible strategy to create this next generation of devices is to controllably introduce discrete atoms (dopants), such as phosphorus atoms, in a silicon crystal. Recent research, where a single phosphorous atom was embedded within epitaxial silicon environment, analysis a possibility of creating a single-atom transistor [4]. Although such an idea looks spectacularly attractive, the side gate architecture used in Ref 4 is not really fit for the purpose of digital applications. In
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