Stress Metrology: The challenge for the next generation of engineered wafers
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Stress Metrology : The challenge for the next generation of engineered wafers Antoine Tiberja, Vincent Paillardb, Cécile Aulnettea, Nicolas Davala, Konstantin K. Bourdellea, Myriam Moreauc, Mark Kennarda and Ian Cayrefourcqa a Soitec, Parc technologique des Fontaines, 38190 Bernin France. b LPST, Paul Sabatier University, 118 route de Narbonne, 31062 Toulouse Cedex 4, France. c Jobin-Yvon, 231 rue de Lille, 59650 Villeneuve d’Ascq, France. ABSTRACT Raman spectroscopy is a powerful and versatile technique for stress measurements in complex stacks of thin crystalline layers at macroscopic and microscopic scales. Using such a technique we show that thick SiGe layers epitaxially grown using graded buffer method are fully relaxed (>95%) at a macroscopic scale but exhibit a small strain modulation at a microscopic scale. For the first time we report the results of Raman micro-mapping of stress distribution in SGOI wafers produced by Smart CutTM technology. We conclude that Smart CutTM is a unique method to manufacture the next generation of engineered wafers that can combine strained and/or relaxed SiGe alloys, Si and Ge films, while keeping their initial strain properties at both scales. It is important to develop Raman spectroscopy tool for in-line process control in fabrication of strained Silicon On Insulator (sSOI) wafers. INTRODUCTION As scale reduction of devices becomes increasingly challenging from a technological point of view, the use of new materials that can improve circuit performance is of great interest. Strained silicon films on insulator are often identified as the engineered wafers needed for the 65 nm CMOS technology node and beyond. They combine the advantages coming from the buried insulator and the strained silicon layers [1]. The wafers can be produced either with (SGOI) or without (sSOI) a relaxed SiGe layer between the strained silicon and the buried insulator films. The unique feature of the Smart CutTM technology enables transfer of a thin film (of essentially any crystalline material) coming from a donor wafer onto an insulating layer to produce the final semiconductor on insulator wafer [2]. Therefore the Smart CutTM technology is a powerful method to manufacture the next generation of engineered wafers combining all sorts of strained and/or relaxed SiGe alloys, sSi and Ge films on insulators. For the development of the sSOI process flow the stress metrology is of critical importance. The experimental technique chosen must determine with high precision the Ge composition and the degree of relaxation of SiGe films as well as the stress induced in the top silicon film. It should be fast, clean-room compatible and be easily adapted in the in-line metrology tool. Standard profiling techniques can not fulfil all these requirements. Spectroscopic Ellipsometry (SE) can measure the SiGe composition due to the refractive index changes [3]. However, SE ability to measure the strain in Si films is still to be demonstrated (the analysis of birefringence effects might address this challenge [4,5])
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