The Electrical Phenomena of Non-planar Structure and Devices using Plasma Doping
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The Electrical Phenomena of Non-planar Structure and Devices using Plasma Doping Jong-Heon Yang, In-Bok Baek, Kiju Im, Chang-Geun Ahn, Sungkweon Baek1, Won-ju Cho2 and Seongjae Lee Future Technology Research Division, Electronics and Telecommunications Research Institute, 161 Gajeong-dong, Yuseong-gu, Daejeon, 305-700, Korea. 1 Dep. of Materials Science and Engineering, Gwangju Institute of Science and Technology. 1 Oruong-dong, Buk-gu, Gwangju, 500-712, Korea. 2 Dep. of Semiconductor and New Materials, Kwangwoon University. 447-1 Wolgye-dong, Nowon-gu, Seoul, 139-701, Korea. ABSTRACT We fabricated narrow fins structures and non-planar MOSFETs like FinFETs and triple-gate MOSFETs using plasma doping with substrate heating under 350℃, and measured their I-V characteristics. Fins and MOSFETs using low-temperature doping process show good current drivability and low subthreshold slope. However, without post high-temperature thermal annealing, this process could not avoid generating defects and traps as well as mobile protons on the gate and gate oxide interface and junctions, and therefore degraded device reliability. The results of ultra-small MOSFET research show possibility of new memory devices with these traps and ions in devices. INTRODUCTION Near future a semiconductor technology will be faced to another red brick wall of quantum mechanical phenomena and a device-level scaling will be too difficult to carry on Moore’s law. Therefore present integration technology using two-dimensional design of planar devices should be replaced by three-dimensional integration scheme with novel structure devices and together with new doping process for these devices. The non-planar SOI-MOSFET devices like FinFET, Tri-Gate, ∏-Gate structures are promise candidates for sub-10 nm MOSFET applications due to their ability to relax the short-channel effects (SCE). A plasma doping process, one of ultrashallow junction technology solutions, has many advantages of high dose, low acceleration voltage and multi-directional dopant implantation because wafers are exposed to high density plasma directly [1,2]. Even without following high-temperature annealing, the plasma doping with substrate heating shows comparable doping efficiency on high aspect ratio, threedimensional structures compared with combination of tilted-angle ion implantation and high-
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temperature post annealing which is widely used in mass production industry. It has been reported that this process was used for junctions of amorphous silicon thin-film-transistor, and in our previous work it was used for planar MOSFET. But it is the first time that used for threedimensional structures or advanced non-planar MOSFET devices [3,4]. Due to its low process temperature proposed new plasma doping is also very attractive to applications of high-k dielectric and metal gate. PLASMA DOPING ON NON-PLANAR STURCTURE The plasma doping system used for this study has two half-cylindrical plates placed opposite to each other on quartz chamber, and they generate high density
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