Tungsten Electrodes Reduce Parasitic Source/Drain Resistance of Poly-Si TFT
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14.94 Å, respectively. Here, the integers in parentheses (n,m) allow a topographical characterization of the chirality of the nanotube in comparison with the lattice vectors that span the graphite lattice. Wilson deems the fact that IINTs with very similar diameters but different morphologies can form in the same SWNT as indicative of significant kinetic control of IINT morphology. Wilson said that his simulations show ”that a class of IINT structures, analogous to those formed by elemental carbon itself, may exist and that an experimental pathway to such structures may lie in the filling of [SWNTs] from the liquid phase.” Two alternate IINT morphologies investigated by Wilson are related to hexagonal or square-net sheets. Energies of geometryoptimized (5,0) IINTs plotted as a function of ion density show double minima, which Wilson attributes to the two morphologies, with the square-net minimum occurring at a higher density than the hexagonal. For (5,2) IINTs formed in small-diameter SWCNTs, the square-net structure is the stable morphology. Wilson said that the presence of multiple energy minima suggests that a pressure-
driven pathway may exist between the square-net and hexagonal IINT morphologies. Indeed, the application of pressure in a simulation of a (14,14) SWNT (diameter, 19.01 Å) filled with bulk molten ions led to the formation of nested, double-walled IINTs—one IINT with morphology (3,2) inside a (9,2) IINT. Wilson said that “this demonstrates that both the [SWCNT] pore diameter and the external pressure have the potential to effectively control both the IINT morphology and the degree of nesting.” STEVEN TROHALAKI
Tungsten Electrodes Reduce Parasitic Source/Drain Resistance of Poly-Si TFT Polycrystalline silicon thin-film transistors (TFTs) are of potential interest for applications in peripheral circuits for active-matrix liquid-crystal displays, but device dimensions must be scaled down in order to improve speed and circuit densities. In the February issue of Electrochemical and Solid-State Letters, H.-W. Zan of the National Chiao Tung University, T.-C. Chang of the National Sun Yat-Sen
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University, P.T. Liu of the National Nano Device Laboratory, and their colleagues have proposed a method for decreasing parasitic resistance of TFTs by the use of tungsten electrodes. The research team from Taiwan created TFTs by conventional methods in which a 30 nm a-Si layer is deposited by low-pressure chemical vapor deposition (LPCVD) on oxidized silicon wafers. After active region patterning, a 60 nm tetraethylorthosilicate (TEOS) oxide layer and subsequently a 300 nm a-Si layer were deposited by LPCVD. The a-Si layer was then recrystallized by solid-phase crystallization at 600°C for 24 h. After defining the gate by reactive ion etching (RIE) and removing the oxide on source/drain (S/D) regions by HF dip, a lightly doped drain implant was performed using phosphorus ions at a dose of 3 × 1013 cm -2. Then, a 200 nm oxide side-wall spacer was formed abu
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