Two causes of source/drain series resistance in bottom-contact pentacene thin-film transistors
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Two causes of source/drain series resistance in bottom-contact pentacene thin-film transistors Makoto Noda, Nobuhide Yoneya, Nobukazu Hirai, Noriyuki Kawashima, Kazumasa Nomoto, Masaru Wada and Jiro Kasahara Fusion Domain Laboratory, Sony Corporation, Higashikojiya Ota-ku, Tokyo 144-0033, Japan ABSTRACT We identified two causes of source/drain (S/D) series resistance (Rs) in bottom-contact (BC) pentancene thin-film transistors (TFTs). One is mixed-phase pentacene grown in the blurrededge region of Au electrodes and the other is the semi-insulating pentacene region between the Au electrode and the carrier-accumulating layer. A novel Au S/D electrode structure with a self-assembled monolayer (SAM) adhesion layer enables direct injection of carriers into the accumulating layer and markedly reduces Rs for unit gate width (RsW) to 6 MΩ µm. BC TFTs with this electrode structure showed extrinsic field-effect mobility as high as 1.1 cm2/Vs. INTRODUCTION Organic thin-film transistors (OTFTs) are receiving considerable attention because they can be fabricated at low temperatures and using low-cost processes which take advantage of organic material’s characteristics such as applicability to spin coating and printing without the need to resort to a vacuum system. Low fabrication temperatures make OTFTs attractive for a variety of flexible electronics applications such as rf identification tags, smart cards and flexible displays. Although significant improvements have been made in the performance of OTFTs in the last few years, it is recognized that one of the factors limiting their performance is source/drain (S/D) series resistance (Rs) [1]. Several studies have been made of the causes of Rs [2], but further work is required to realize high performance OTFTs with a short gate length. TOP-CONTACT (TC) AND BOTTOM-CONTACT FABRICATED BY SHADOW-MASK PROCESS
(BC)
PENTACENE
TFT
Figure 1 shows a schematic cross section of TC and BC pentacene TFTs. A heavily doped n -type silicon substrate was used for the gate electrodes. Thermally grown silicon dioxide 150 nm thick served as the gate insulator. Prior to deposition of the pentacene layer, the gate dielectric surface was treated with 1,1,1,3,3,3-hexametyldisilazane (HMDS). Gold source and ++
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drain electrodes were deposited through a shadow mask by thermal evaporation before (see Fig. 1(a)) or after (see Fig. 1(b)) active layer deposition for the BC or TC TFT. The pentacene active layer was deposited through a shadow mask by thermal evaporation at a rate of ~0.05 nm/s at a substrate temperature of 60 oC. Gate lengths Lg of 50, 100, 300, and 1000 um and a gate width Wg of 3000 um were investigated. source
drain
pentacene source drain
pentacene
SiO2
SiO2
n+ - Si
n+ - Si gate electrode
gate electrode
(a)
(b)
Fig. 1. Schematic cross section of a BC pentacene TFT (a) and a TC pentacene TFT (b).
10
0
2
Carrier mobility ( cm /Vs )
Figure 2 shows the dependence of extrinsic field-effect carrier mobility in the linear region on Lg at the effective gate-sourc
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