VHDL Coding Styles and Methodologies
VHDL Coding Styles and Methodologies, Edition is a follow up book to the first edition of same book and to VHDL Answers to Frequently Asked Questions, first and second editions. This book was originally written as a teaching tool for a VHDL training cours
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VHDL Coding Styles and Methodologies Second Edition
Ben Cohen
KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW
CD-ROM only available in print edition. eBook ISBN: 0-306-47681-9 Print ISBN: 0-7923-8474-1
©2002 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print ©1999 Kluwer Academic Publishers Dordrecht All rights reserved No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: and Kluwer's eBookstore at:
http://kluweronline.com http://ebooks.kluweronline.com
CONTENTS 1.0 VHDL OVERVIEW AND CONCEPTS 1.1 WHAT IS VHDL 1.2 LEVEL OF DESCRIPTIONS 1.3 METHODOLOGY AND CODING STYLE REQUIREMENTS 1.4 VHDL TYPES 1.5 VHDL OBJECT CLASSES 1.5.1 Constant 1.5.2 Signal and Variable 1.5.3 File 1.6 VHDL DESIGN UNITS ENTITY 1.6.1 1.6.1.1 Style 1.6.1.1.1 Comment 1.6.1.1.2 Header 1.6.1.1.3 Generics 1.6.1.1.4 Indentation 1.6.1.1.5 Line length 1.6.1.1.6 Statements per line 1.6.1.1.7 Declarations per line 1.6.1.1.8 Alignment of declarations 1.6.1.2 Entity Ports
1.6.2
ARCHITECTURE
1.6.2.1
Process
1.7 COMPILATION, ELABORATION, SIMULATION 1.7.1 Compilation Example 1.7.2 Simulation Example 1.7.3 Synthesis Example
2.0 BASIC LANGUAGE ELEMENTS 2.1 LEXICAL ELEMENTS 2.1.1 Identifiers 2.1.1.1 2.1.1.2
2.1.1.3 2.1.1.4
Port Identifiers Identifier Naming Convension Accessing Identifiers Defined in Packages Capitalization
2.2 SYNTAX 2.2.1 Delimiters 2.2.2 Literals 2.2.2.1 2.2.2.2 2.2.2.3 2.2.2.4 2.2.2.5
2.2.3
Decimal literals Based literals Character literals String literals Bit string literals
Operators and Operator Precedence Logical operators Relational Operators Shift Operators The Concatenation "&" Operator
2.2.3.1 2.2.3.2 2.2.3.3 2.2.3.4
1 1 2 3 4 5 6 7 9 9 10 10 11 12
12 13 13
13 13 14 14
16 17
20 23 24 25 29
29 29 31 32 36 37
38 39 40 40
40 40 41 41
42 43 43 44 46
vi
VHDL Coding Styles and Methodologies
2.2.3.5
Remainder and Modulus
2.3 TYPES AND SUBTYPES 2.3.1 Scalar Type Integer Type and Subtypes 2.3.1.1 2.3.1.2 Enumeration Types 2.3.1.2.1 User Defined Enumeration Types 2.3.1.2.2 Predefined Enumeration Types 2.3.1.2.3 Boolean Type Physical types 2.3.1.3 Distinct Types and Type Conversion 2.3.1.4 Real type 2.3.1.5
2.3.2
Composite
2.3.2.1 Arrays 2.3.2.1.1 One Dimensional Arrays 2.3.2.1.2 Unconstrained Array Types 2.3.2.1.3 Multi-dimensional Array types 2.3.2.1.4 Anonymous Arrays 2.3.2.1.5 Implicit Functions for Array Declarations 2.3.2.1.6 Array Slices and Ranges 2.3.2.2 Records
2.3.3 Access Type 2.4 FILE 2.5 ATTRIBUTES 2.6 A LIASES
3.0 CONTROL STRUCTURES 3.1 EXPRESSION CLASSIFICATION 3.2 CONTROL STRUCTURES 3.2.1 The "if" Statement 3.2.2 The Case Statement 3.2.2.1
3.2.3 3.2.4 3.2.5
Rules for the Case Statement
Latch Inference Register Inference Loop Statement
3.2.5.1 The Simple Loop 3.2.5.2 The while loop The for loop 3.2.5.3 3.2.5.3.1 for loop Rules
4.0 DRIVERS
49 51 51 54
