Rapid Prototyping of Field Programmable Gate Array-Based Discrete Cosine Transform Approximations
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Rapid Prototyping of Field Programmable Gate Array-Based Discrete Cosine Transform Approximations Trevor W. Fox Department of Electrical and Computer Engineering, University of Calgary, 2500 University Drive N.W., Calgary, Alberta, Canada T2N 1N4 Email: [email protected]
Laurence E. Turner Department of Electrical and Computer Engineering, University of Calgary, 2500 University Drive N.W., Calgary, Alberta, Canada T2N 1N4 Email: [email protected] Received 28 February 2002 and in revised form 15 October 2002 A method for the rapid design of field programmable gate array (FPGA)-based discrete cosine transform (DCT) approximations is presented that can be used to control the coding gain, mean square error (MSE), quantization noise, hardware cost, and power consumption by optimizing the coefficient values and datapath wordlengths. Previous DCT design methods can only control the quality of the DCT approximation and estimates of the hardware cost by optimizing the coefficient values. It is shown that it is possible to rapidly prototype FPGA-based DCT approximations with near optimal coding gains that satisfy the MSE, hardware cost, quantization noise, and power consumption specifications. Keywords and phrases: DCT, low-power, FPGA, binDCT.
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INTRODUCTION
The discrete cosine transform (DCT) has found wide application in audio, image, and video compression and has been incorporated in the popular JPEG, MPEG, and H.26x standards [1]. The phenomenal growth in the demand for products that use these compression standards has increased the need to develop a rapid prototyping method for hardwarebased DCT approximations. Rapid prototyping design methods reduce the time necessary to demonstrate that a complex design is feasible and worth pursuing. The number of logic resources and the speed of field programmable gate arrays (FPGAs) have increased dramatically while the cost has diminished considerably. Designs can be quickly and economically prototyped using FPGAs. A methodology that can be used to rapidly prototype DCT implementations with control over the hardware cost, the quantization noise at each subband output, the power consumption, and the quality of the DCT approximation would be useful. For example, a DCT implementation that requires few FPGA resources frees additional space for other signal processing functions, which can permit the use of a smaller less expensive FPGA. Also near
exact DCT approximations can be obtained such that the hardware cost and power consumption requirements are satisfied. A rapid prototyping methodology for the design of FPGA-based DCT approximations that can be used to control the quality of the DCT approximation, the hardware cost, the quantization noise at each subband output, and the power consumption has not been previously introduced in the literature. A method for the design of fixed point DCT approximations has recently been introduced in [2], but it does not specifically target FPGAs or application-specific integrated circuits (ASICs). The method discussed in [2] can be used
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