Multiple Constant Multiplication Optimizations for Field Programmable Gate Arrays
This work covers field programmable gate array (FPGA)-specific optimizations of circuits computing the multiplication of a variable by several constants, commonly denoted as multiple constant multiplication (MCM). These optimizations focus on low resource
- PDF / 3,458,549 Bytes
- 225 Pages / 419.528 x 595.276 pts Page_size
- 54 Downloads / 201 Views
Multiple Constant Multiplication Optimizations for Field Programmable Gate Arrays
Multiple Constant Multiplication Optimizations for Field Programmable Gate Arrays
Martin Kumm
Multiple Constant Multiplication Optimizations for Field Programmable Gate Arrays With a preface by Prof. Dr.-Ing. Peter Zipf
Martin Kumm Kassel, Germany Dissertation of Martin Kumm in the Department of Electrical Engineering and Computer Science at the University of Kassel. Date of Disputation: October 30th, 2015
ISBN 978-3-658-13322-1 ISBN 978-3-658-13323-8 (eBook) DOI 10.1007/978-3-658-13323-8 Library of Congress Control Number: 2016935387 Springer Vieweg © Springer Fachmedien Wiesbaden 2016 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. Printed on acid-free paper This Springer Vieweg imprint is published by Springer Nature The registered company is Springer Fachmedien Wiesbaden GmbH
Preface As silicon technology advances, field programmable gate arrays appear to gain ground against the traditional ASIC project starts, reaching out to form the mainstream implementation basis. Their predefined structures result in an essential inefficiency, or performance gap at all relevant axes, i.e. clock frequency, power and area. Thus, highly optimised system realisations become more and more important to use this technology at its best. Microarchitectures and their adaptation to the FPGA hardware, combined with an optimal matching of model structures and FPGA structures, are two points of action where engineers can try to get optimally balanced solutions for their designs, thus fighting the performance gap towards the ASIC reference. While microarchitecture design based on the knowledge of FPGA structures is located in the domain of traditional hardware engineering, the mapping and matching is based on EDA algorithms and thus strongly related to computer science. Algorithms and the related sophisticated tools are permanently in short supply for leading edge optimisation needs. Martin’s dissertation deal
Data Loading...
