Relationship Between Graded Layer Structures and Defects in Silicon-Germanium Virtual Substrates
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RELATIONSHIP BETWEEN GRADED LAYER STRUCTURES AND DEFECTS IN SILICON-GERMANIUM VIRTUAL SUBSTRATES Kazuki Mizushima, Ichiro Shiono, Kenji Yamaguchi, and Naoki Muraki1 Central Research Institute, Mitsubishi Materials Corporation, 1-297 Kitabukuro-cho, Omiya,Saitama 330-8508, Japan 1 Mitsubishi Materials Silicon Corporation, 314 Nishisangao, Noda, Chiba 278-0051, Japan ABSTRACT Silicon-germanium virtual substrates have been synthesized by low-pressure chemical vapor deposition. We obtained threading dislocation densities ranging from 105 to 106 cm-2, surface roughness ranging from 1.5 to 4 nm, and also cross-hatch pattern densities, depending on the grading rate and top layer germanium composition. For the typical sample, which has a linear-graded structure with a grading rate of 20%/µm, and germanium composition of 30 % at the top layer, we obtained dislocation densities of about 106 cm-2 and root mean squared surface roughness of about 3 nm. The obtained dislocation densities are equivalent with the virtual substrates synthesized by ultra-high vacuum system. On the other hand the surface roughness is superior to the typical reported values. In this study three kinds of structures, i.e. linear-graded, stepwise, and graded-step structures, were considered. We found the defects are effectively reduced by introduction of an optimum number of steps in the graded layer.
INTRODUCTION A silicon-germanium virtual substrate consists of two epitaxial layers on a silicon substrate, i.e., a compositionally graded Si1-xGex layer (graded layer) and a constant composition Si1-xGex over layer (buffer layer), as shown in figure 1. Because the threading dislocation density in the buffer layer is drastically reduced, by virtue of the graded layer, we can obtain a relaxed Si1-xGex layer with low defect density on a silicon substrate [1,2]. Defect-free virtual substrates might provide a favorable way to fabricate strained-silicon field-effect transistors (FET) [3]. However, high threading dislocation density and rough surface morphology limit the capability of the substrate. [4,5] Reported threading dislocation densities and surface roughness of virtual substrates range from 104 to 107 cm-2, and about 5 to 20 nm, respectively. Those values are too high for realistic large-scale integration (LSI). Virtual substrates are usually synthesized by using ultra-high vacuum systems such as molecular beam epitaxy (MBE), gas-source molecular beam epitaxy (GSMBE), and ultra-high vacuum chemical vapor deposition (UHV-CVD). On the other hand, the number of reports on the virtual substrates synthesized by low-pressure chemical vapor deposition (LPCVD) is limited. Nevertheless, it is a potential candidate for commercial production process of the substrate. In this study we employed LPCVD in order to examine capability of the process for the virtual substrate.
P11.1.1
strained-Si
20 nm 0.75 µm 1.5 µm
SiGe buffer layer SiGe graded layer Si wafer
30 0 Ge (%)
Figure 1. Schematic representation of a virtual substrate. To date, in order to reduce defect
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