Reliability Estimation of Logic Circuits at the Transistor Level
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Reliability Estimation of Logic Circuits at the Transistor Level H. Jahanirad1 Received: 20 October 2019 / Revised: 23 October 2020 / Accepted: 27 October 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract The reliability evaluation of logic circuits is an essential step in the computer-aided design flow of emerging integrated circuits (IC). Due to the increased process variation effects in submicron IC technologies, reliability evaluation should include the transistor-level faults’ modeling and analysis. In this paper, a two-step reliability evaluation method was developed. In the first step, the gate error probability (in a matrix form) was computed based on transistor fault modeling. In the second step, the circuit’s graph was traversed in topological order. Meanwhile, for each gate, the probability of the gate’s output to be in 16 possible states was computed using the gate error probability matrix (calculated in the first step) and the corresponding gate inputs’ probability matrices. The reliability of the circuit’s outputs was extracted from the related 16-state probability matrix. Furthermore, the reconvergent fan-out problem was handled using the concept of correlation coefficients. Various simulations were performed on ISCAS 89 and LGSynth91 benchmark circuits. Compared with MonteCarlo as a reference method, the results indicated a < 3% average error on reliability estimation. Furthermore, the estimation error and algorithm runtime of the proposed method significantly decreased in comparison with some state-of-the-art methods. Keywords Reliability · Combinational circuits · Correlation coefficients · Faults and errors · Transistor-level implementation
1 Introduction The reliability evaluation of submicron integrated circuits has become an important issue due to the significant probability of fault occurrence in such devices [10]. Complementary metal–oxide semiconductor (CMOS) transistors show some randomness in
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H. Jahanirad [email protected] Department of Electrical Engineering, University of Kurdistan, Pasdaran St., Sanandaj 66177-15175, Iran
Circuits, Systems, and Signal Processing
their features (e.g., the transistor gate length or threshold voltage) throughout the chip [28]. The main reason for such a probabilistic behavior is imprecision in the fabrication process which leads to the generation of more defects in the fabricated transistors. Such defects frequently generate various types of transistor-level faults such as stuck ON or stuck OFF [3, 4, 24, 29]. In emerging technologies (such as CNTFET), substantial non-deterministic behavior causes a higher failure rate in the implemented logic circuits [22, 30]. On the other hand, in mission-critical applications (e.g., aerospace), there is a large amount of external upsets (e.g., energetic particles) which may make the chip faulty. These challenges highlight the importance of reliability analysis in the logic circuit design flow [9, 17, 30]. Von-Neumann proposed the first model of noise (error) behavior in
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