Comparative Study on Wafer-Level and Package-Level Electromigration Reliability for Sub-Quarter Micron Logic Devices
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Comparative Study on Wafer-Level and Package-Level Electromigration Reliability for Sub-Quarter Micron Logic Devices Young B. Park and Duk W. Lee System IC R & D Center, Hyundai Electronics Co., Ltd., Cheongju, 360-480, Korea ABSTRACT The effects of Al underlayer between Ti and TiN on the electromigration (EM) lifetime of Al stack film were compared by the package-level and conventional wafer-level EM tests. The higher EM resistance of the Al stacks prepared with Ti underlayer can be best explained by their better Al (111) texture and grain size distribution than those with TiN underlayer. The surface roughness of the underlayer is related to the grain size distribution and surface roughness of Al film. INTRODUCTION It has been observed that EM lifetime of Al-0.5%Cu films is highly dependent on the median grain size, the distribution of grain sizes, and the texture [1,2]. It was proposed the empirical relationship between the MTTF (Mean-Time-To-Failure) and the microstructure of Al-0.5%Cu films as [1]; é I (111) ù S MTTF ∝ 2 log ê ú σ êë I (200 ) úû
3
(1)
where S is the median grain size, is the log-normal standard deviation of the grain size, and I(111) and I(200) are X-ray intensities of (111) and (200) diffractions, respectively. Al-Cu alloy stacked with Ti or TiN have been widely used as Si-based integrated circuit metallization. Formation of Al intermetallic compound such as TiAl3 alloy above or below the Al metal stacked with Ti is known to be effective in preventing EM related failures [3-5]. Longer EM lifetime can be explained by making the assumption that TiAl3 could act as an alternative current pass [3] or by assuming that the migration of Al atoms could be suppressed at the TiAl3\Al interface [6]. Formation of Ti-Al reaction layer in Al stack with Ti underlayer reduces the cross section of Al portion which is the main path of electrical current during EM testing. By the way, there would be nearly no loss of Al portion in Al stack with TiN underlayer, which makes the effective current density of Al portion larger for TiN than Ti underlayer. So there were some inconsistencies in the effects of Ti and TiN underlayer on EM resistance of Al stack [4-8]. Also, L9.3.1
although substantial studies have been performed on the effect of Ti or TiN underlayer on EM reliability of Al stack [3-8], there are few well-documented systematic studies on the comparison between Ti and TiN underlayer on the EM reliability, which were carried out in this study. And the package-level and conventional wafer-level EM tests were compared each other. The conventional wafer-level EM test method used a little higher current density and the same ambient temperature used in the package-level EM test for cost saving and shorter test time. EXPERIMENTAL Seven-level metallization systems with a single-level Metal 1 EM test structure were fabricated using the procedure described below. Plasma enhanced chemical vapor deposited (PECVD) oxide of 700nm was prepared on P-type Si wafer. A bottom-Ti or TiN (10nm)\Al-0.5%Cu (350nm)\Ti (5nm)\TiN
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