Removal of TaN/Ta Barrier with Variable Selectivity to Copper and TEOS
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Removal of TaN/Ta Barrier with Variable Selectivity to Copper and TEOS Jinru Bian, John Quanci, and Matthew VanHanehem Rodel Inc., Newark, DE, Tel: (302) 366-0500 Abstract Highly selective 2 step copper slurries developed by Rodel have efficient barrier (TaN) polishing rates at extremely low down force (1000 Å/min at one psi, and 2000 Å/min at 3 psi). Removal rates of dielectrics (TEOS or low k CDO) can be independently adjusted from zero to nearly any designed value and copper removal rates can be independently controlled from 20 to 500 Å /min, while maintaining the high barrier removal rates. In addition, zero loss of low-k dielectric capping layers has been demonstrated, and zero loss of high metal density (90%) domain of pattern wafers with 30 seconds overpolishing has been demonstrated. Experiments also show that the high selectivity is a true CMP effect and not due to static etching. nd
Introduction Copper (Cu) chemical mechanical polishing (CMP) employs a two-step polishing process. A first step Cu slurry is used to remove both the bulk copper film layer and any remaining Cu residue on a wafer. The second step CMP process employs slurry that is used for removal of the barrier film, such as tantalum (Ta) or tantalum nitride (TaN). Both slurries are designed to minimize dishing and erosion. During the second step barrier removal, dielectric loss will lead to severe erosion, especially for the high-density metal line domain where the local down force is believed to be higher than its nominal value. At the same time, excess Cu removal from copper lines during second step polishing can lead to increased copper dishing compared to the results after first step polishing. In order to eliminate dielectric loss and erosion, and to minimize dishing of copper lines, a 2nd step slurry with selective removal of the barrier layer to the dielectric material and to copper is desired. Ideally, the first step process should achieve two goals: (1) a zero topography, i.e. fully planarized surface; (2) zero copper residuals left on the surface of the dielectric. In reality, limited first step planarization efficiency can lead to metal line dishing and copper residuals. Depending on the difference between the dishing values from first step CMP and the desired topography tolerance, manufacturers may require some correction of the first step topography in addition to barrier removal during second step polishing. Thus, the second step slurry should have a high barrier removal rate, an adjustable dielectric removal rate to correct topography, and a minimal copper rate to clear any first step residuals. In the case of low-k dielectrics, there can be additional capping layers such as SiC, TEOS SiO2 or Si3N4 under the barrier layer and above the low-k dielectric film. It would be advantageous to have selective removal of the barrier layer to capping material and to Cu. In addition, low-k materials often have very low mechanical stress tolerance, especially for porous low-k dielectrics. Thus, the industry desires a second step CMP
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